# Parallel port schematic

```          THE TYPICAL SCHEMATIC OF ORIGINAL IBM PC PARALLEL PORT
Text and Two Page ASCII-Matic (ASCII Schematic)
copyright (c) 1996 Richard Steven Walz for the Public Domain
```

We shall look at these ports by number and binary conversion in address bit form. Note: XX means bits that are either 1 or 0 for the needed three successive I/O port address numbers.

```           [ 3] [ 7]  [8,9,A, and B possible, but 37BH not used]
378H-37BH = 11  0111  10XX ( = 888 thru 891 decimal, but 891 not used.)

[ 2] [ 7]  [8,9,A, and B possible, but 27BH not used]
278H-27BH = 10  0111  10XX ( = 632 thru 635 decimal, but 635 not used.)

[ 3] [ B]  [C,D,E, and F possible, but 3BF not used]
3BCH-3BFH = 11  1011  11XX ( = 956 thru 959 decimal, but 959 not used.)
```
For the sake of understanding how the PC talks to the parallel port pins, I here furnish a logical schematic of a typical Standard Parallel Port, found on original IBM PC's and backward compatible even today in the most advanced machines, though implemented on so-called Super-I/O IC's:
```--
Richard Steven Walz   rstevew@armory.com  ftp://ftp.armory.com/~rstevew/
Electronics!: 600 files/37 directories!! http://www.armory.com/~rstevew/
```

Note that a simple bi-directional parallel port can be created by cutting or lifting the pin 1 of the data latch 74LS374 and connecting it with a jumper to pin 15 of the 74LS174 of the control latch. Also make sure the input to that latched bit into pin 14 of the 74LS174 is connected to the data bit D5 of the PORT INNER DATA BUS off pin 13 of the 74LS245 bidirec- tional bus driver on the ISA BUS! Then set bit 5 of the control or base+2 port logic HI and the output of the data latch will be tristated, and the data latch read-back buffer can read any external TTL signals! Set bit 5 to logic LO or a value of 0 to return the output of the data latch, but only when outside data voltages have been removed!!

```
|                                                                                                                                       |NAME- PIN
|                      ______  ____                                                                 _____        DATA LATCH       |
ISA |                     /     /--PORT--[#1]                                                       | 3|     | 2---+--------------->D0|DATA0--2
BUS |        1 +--DIR----<     (    ___ (see below)                                                 | 4|OCTAL| 5---)-+------------->D1|DATA1--3
|        __|__        \_____\---IOR--[#2]                                                       | 7|TRI-S| 6---)-)-+----------->D2|DATA2--4
A9 |D0----2|     |18|                                                                    ++==/8/==>| 8|LATCH| 9---)-)-)-+--------->D3|DATA3--5
A8 |D1----3|74LS-|17|                                                                    ||        |13| =/=>|12---)-)-)-)-+------->D4|DATA4--6
A7 |D2----4| 245 |16|                                                                    ||        |14|74LS |15---)-)-)-)-)-+----->D5|DATA5--7
A6 |D3----5|     |15|                     PORT INNER                         PORT INNER  ||        |17|'374 |16---)-)-)-)-)-)-+--->D6|DATA6--8
A5 |D4----6|<===>|14|==========/8/=========<=====>=========/8/====<DATA8>====<==>==/8/==++        |18|_____|19---)-)-)-)-)-)-)-+->D7|DATA7--9
A4 |D5----7|     |13|                     DATA BUS                          DATA BUS    ||           11| O 1     | | | | | | | |    |
A3 |D6----8|     |12|                                                       +-----------))------CP-----+ |       | | | | | | | |    |
A2 |D7----9|_____|11|                                                       |           ||         __    |       | | | | | | | |    |
|        _ O 19                                                          |           ||  +--\\--OE----+ [#3]* | | | | | | | |    |
|        E_|_GND            ________________________________             |           || _|_GND     _____      | | | | | | | |    |
|          -               | DUAL 2 to 4 DEMUX  _____       | 7   ___    |           ||  -     |18|     | 2<--+ | | | | | | |D0  |
|                        13|        74LS155    |     |O-Q0a-|O--->RDE>---)--------+  ||        |16|OCTAL| 4<----+ | | | | | |D1  |
A31 |A0-----------------A0-----|A0----+            |  2  |      | 6   ___    |        |  ||        |14|TRI-S| 6<------+ | | | | |D2  |
A30 |A1-----------------A1-----|A1--+ |         __ | to  |O-Q0a-|O--->RSE>---)-----+  |  ++<==/8/==|12|BUFR | 8<--------+ | | | |D3  |
A29 |A2-0-|>O-1---|           3|    | | +--Ea1-|  \|  4  |      | 5   ___    |     |  |  ||        | 9|<=== |11<----------+ | | |D4  |
A28 |A3-1-----1---|            |    | | |      |   |DEMUX|O-Q2a-|O--->RCE>---)--+  |  |  ||        | 7|74LS |13<------------+ | |D5  |
A27 |A4-1-----1---|---.  ____  |    | | | +---O|__/|  a  |      | 4          |  |  |  |  ||        | 5|'244 |15<--------------+ |D6  |
A26 |A5-1-----1---|    \ PORT 2|___ | | | |        |_____|O-Q3a-|O--NC       |  |  |  |  ||        | 3|_____|17<----------------+D7  |
A25 |A6-1-----1---|NAND |O--+--|Ea2-)-)-)-+          | |        |            |  |  |  |  ||         __1 O O 19__  DATA LATCH         |
A24 |A7-0-|>O-1---|    /    |14|___ | +-)------------+ |        |            |  |  |  |  ||         OE  | |   OE  READ-BACK BUFFER   |
A23 |A8-1-----1---|---`     +--|Eb1-)---)-+        A0| |A1      |            |  |  |  +--))-------------+-+                          |
A22 |A9-1-----1---|  ____   |  |    +---)-)----------)-+        |            |  |  |     ||            _____                         |
| 378H->3FFH  |  PORT [#1] |        | |         _|_|_       | 9   ___    |  |  |     ||           |ASSRT|<--------------------<S3|/ERROR-15
|             | ___        |        | |     __ |     |O-Q0b-|O--->WDE>---+  |  |     ||           |TRI-S|<--------------------<S4|/SLCTI-13
A11 |AEN-0-|>O-1--| AEN        |        | +---O|  \|  2  |      | 10            |  |     ++<===/5/===||<=== |<--------------------<S5|/PE----12
|___                     15|___     |      |   | to  |O-Q1b-|O--NC          |  |     ||  __       |BUFRS|<-------+------------<S6|/ACK---10
B13 |IOW-----------------------|Eb2-----)-----O|__/|  4  |      | 11  ___       |  +-----))--OE------O|_____|<--O<|--)-----------<-S7|BUSY---11
|___                      1|        |          |DEMUX|O-Q3b-|O--->WCE>---+  |        ||    ____          ___     | STATUS INPUTS |
B14 |IOR-0---+---|>O-1----IOR--|Ea1-----+          |  b  |      | 12         |  |  +-----))----IRQ7---------(ACK)----+               |
|        |  ___            |                   |_____|O-Q3b-|O--NC       |  |  |     ||            _____     CONTROL LATCH       |
|      [#2] IOR            |________________________________|            |  |  |     ||        | 3| HEX | 2----|/>O---*------>-C0|/STB----1
|                                                                        |  |  |     ||        | 4|LATCH| 5----|/>O---)-*---->-C1|/AUTO--14
|                      /|                               ___      ____    |  |  |     ++==/6/==>| 6| =/=>| 7----|/>----)-)-*--->C2|/INIT--16
B21 |IRQ7<---------------O< |---------------------------(S6 ACK)----<IRQ7<---)--)--+     ||        |11|74LS |10----|/>O---)-)-)-*>-C3|/SLCTO-17
|                      \|  NOTE: --|/>----*     ==>                      |  |        ||        |13|'174 |12------+C4  | | | |    |
|  NOTE: --|>O-- IS    |   AND:  --|/>O---*     ==>                      |  |        ||        |14|_____|15-C5nc |    | | | |    |
|   INVERTER SYMBOL    |   PULLED-UP OPEN-COLLECTOR                      |  |        ||      ___   |9  |1  [#3]* |    | | | |    |GNDS---18
|                      |   BUFFERS AT CONTROL LATCH               ___    +--)--------))------WCE---+CP |__       |    | | | |    |   A   19
B2 |RESET>----------------)-------------------------------|>O------->RST>------)--------))----------------+MR       |    | | | |    |   L   20
|                      |                                                    |        ||            _____         |    | | | |    |   L   21
|NC: No Connection     | DEFINITIONS: -RDE = READ DATA ENABLE (LO)          |        ||           |ASSRT|<--O<|--)----+ | | |C0  |   G   22
NCs:|A: 1,10,12-21         |              -RSE = READ STATUS ENABLE (LO)        |        ||           |TRI-S|<--O<|--)------+ | |C1  |   N   23
|B: 4-9,11-12,15-20    |              -RCE = READ CONTROL ENABLE (LO)       |        ++<===/5/===||<=== |<-------)--------+ |C2  |   D   24
|B: 22-28,30           |              -WDE = WRITE DATA ENABLE (LO)         |               __    |BUFRS|<--O<|--)----------+C3  |GNDS-+-25
|                      |              -WCE = WRITE CONTROL ENABLE (LO)      +---------------OE---O|_____|<-------+ CONTROL LATCH |     |
Vcc |B3,B29                |                                                                                         | READ-BACK     |    _|_
GND |B1,B10,B31            +----INT ENABLE-------(C4 INT EN)--------<INTE<-------INT ENABLE-------------------C4-----+ BUFFER        |     -
|

```

The orignal version of this document can be found at ftp://ftp.armory.com:/pub/user/rstevew/LPT/lptskmtc.asc