TTL and CMOS

[ghinaiya_rajesh]

Dear sir,
What is the difference between TTL and CMOS logic family? What are the
advatages of each? Which one is preffered?

with regards
Rajesh

[Tomi Engdahl]

What is the difference between TTL and CMOS logic family?

TTL and CMOS logic families are manufactured by completely different process and have different kind of electrical characteristics (for example different logic 0 and ligic 1 voltage ranges).

Historically the TTL (Transistor-Transistor logic) series has been very important and widely used. TTL is high speed, low power, and economical.
TTL logic is based on bipolar transistors as the active elements inside ICs.
The TTL family's characteristics have made it the most popular logic family industry. Although, it does not stand out in any one area its speed and reliability have made it popular.
Acceptable values for logic 0 is in range 0-0.8 V and for logic 1 the voltage range is normally 2.0-5.0 V.
Typical power dissipation of standard TTL is 10 mW per gate. The propagation delay is typically 10 ns. Noise margin is 0.4 V. Typical fan-out is 10.
The standard operating voltage or TTL logic is 5V (+-10%).
Nowadays there exist also TTL families that operate at lower voltage (for example low voltage TTL operating at 3.3V).
Standard TTL level ICs work on approximate the following voltage levels:
Logic low: 0-0.4V
Logic high: 2.4-5V
Typical voltage levels:
OUTPUT:
LOGIC 1: 2.7-5V
LOGIC 0: 0-0.4V
INPUT:
LOGIC 1: 2-5V
LOGIC 0: 0-0.8V


CMOS families are extremely important and widely used, especially in large scale integrated circuits (e.g. microprocessors). CMOS is low power (significantly lower than TTL). Older CMOS families were slow, newer ones have a speed comparable to TTL. The CMOS logic ICs are based on MOSFETs. In CMOS (Complementary Metal-Oxide Semiconductor) technology, both N-type and P-type field effect transistors are used to realize logic functions. CMOS logic has very high input input resistance.
Loads connected to ICs affect switching speed (due to channel capacitance).
CMOS is very popular digital IC family nowadays. Its low power consumption and high fan-out make it a desirable choice when designing a circuit. CMOS's primary disadvantage is that it cannot be packed as densely as TTL, this is due to the fact that each transistor in a CMOS circuit is actually made from a PMOS transistor and an NMOS transistor.
Traditional CMOS logic is normally powered by 5..12V power source (typically accepts 3-16V DC power source). There are also variations that accept smaller voltage range (targeted usually for 5V or 3.3V operation).
Typical power dissipation of CMOS is 0.1 mW per gate. The propagation delay is typically 25 ns. Typical fan-out is 50.
CMOS logic IC very sensitive to ESD. Most modern CMOS chips include two protection diodes at every I/O pad, wired as clamps. These diodes limit the input voltage from going much higher than VCC or lower than ground.
There is one unfortunate effect that can happen with many CMOS components: latch-up. SCR latch-up is a parasitic phenomena that has existed in circuits fabricated using bulk silicon CMOS technologies. The latch-up mechanism, once triggered, turns on a parasitic SCR internal to CMOS circuits which essentially shorts VCC to ground. This generally destroys the CMOS IC or at the very least causes the system to malfunction. Latch-up most commonly can be turned on by by applying a voltage greater than Vcc or less than ground any input or output, which forward biases the input or output diodes. These diodes can act as the gate to the parasitic SCR.
For CMOS logic operating with 5V power source the logic voltage levels are typically following:
OUTPUT
LOGIC 1: around 4.5-5V
LOGIC 0: around 0-0.5V
INPUT
LOGIC 1: 3.5-5V
LOGIC 0: 0-1V




More useful information on the topic can be found at following pages
http://www.epanorama.net/links/digital.html
http://engnet.anu.edu.au/DEcourses/engn ... node9.html

[Guest]

Dear sir,
What is the difference between TTL and CMOS logic family? What are the
advatages of each? Which one is preffered?

with regards
Rajesh

including above all , normally ttl are used for experimental purposes in collages and universities as it is much more cheaper than CMOS, CMOS is used mainly in industry and commercially.
Also CMOS comes in two verities one that has source vlotage requirement of 12V dc and the other that has 5V requirement, although in collages and universities the 12V type is used again because it is lower price
If you are not designing a power sensitive and delay/time sensitive very large circuit than their is no need to use CMOS, ttl will do JUST FINE and you wont feel any differience in performance