Saleae logic analyzers seem to have it all: good sampling rates, convenient protocol decoding, and plenty of channels – but not a good way to set rising or falling-edge triggering. [James] found this rather inconvenient when debugging embedded devices, and shared a workaround that replicates these simple triggering modes.

Crucially, the logic analyzer’s software has a repeated triggering mode that fires when the protocol decoder detects a preset value. [James] used a clever trick to turn this into a rising-edge trigger: he set up a simple parallel analyzer, and set the signal in question as both the sampled channel and the clock signal. Since he wanted to detect the rising edge, he set the clock mode accordingly. Next, he loaded the simple parallel decoder’s trigger configuration and set it to detect a value of one, the value of a high signal. When he ran the simple parallel trigger, every rising edge of the input signal would trigger the clock to check for a high value on the line, in turn triggering the analyzer.

Saleae Logic Analyzer – “Normal” trigger mode workaround
https://www.youtube.com/watch?v=VVu-2U9KXYE

This plugin is for use in the Saleae Logic program to decode captured data from any SPDIF Interface.

LICENSE is GPLv2

So far I’ve built/run it on 64 bit windows and linux.

For reliable capture of 48kHz spdif, capture at 25 MHz For reliable capture of 192kHz spdif, capture at 100 MHz

Use the browse button to select the directory that contains your compiled custom protocol analyzer.

It was finally time to find a better solution for debugging the electronic leadscrew hardware and firmware, so I reached out to Saleae about getting a new logic analyzer for the project. This video is that story. We’ll also unbox and try it out.

Original Logic:
Datasheet: ​https://downloads.saleae.com/specs/Logic+Tech+Specs.pdf