Editor’s note: Low power IC solutions are in great demand with the rapid advancement of handheld devices, wearables, smart cards and the IoT bringing a massive amount of new products to market that all have the same primary need: Powering the device as long as possible between the need to re-charge the batteries. Ambiq Micro came on the scene four years ago with the goal of creating ultra-low power semiconductor solutions like microcontrollers, real-time clocks, and advanced power management. This white paper shows a 40 year old revived, innovative technique they use in the design of their ICs.

While reducing energy consumption is critically important throughout the electronics industry, the question is: how should that goal be achieved? Ambiq Micro’s approach moves beyond the incremental improvements that other semiconductor companies have taken and makes revolutionary advances through a unique approach to the problem: sub-threshold circuit design.

Energy is consumed in two fundamental ways: as leakage, when a circuit’s state isn’t changing, and dynamically as internal nodes are charged up and down. For realistic circuits in operation, dynamic power dominates – especially for the higher power supply voltages used in most designs today

Traditional digital designs use the transistor state – “on” or “off” – as a critical concept for implementing logic. Analog designs likewise assume that a transistor is “on” to some controlled degree, using it for amplification. But sub-threshold operation means that none of the voltages in the chip rise above the threshold voltage (Vth), so the transistors never turn on. Even a logic “high” voltage keeps the transistors “off.” This means that completely new design approaches are required.

Sub-threshold design isn’t a new concept. As far back as the 1970s, Swiss watchmakers noticed the potential of operating select transistors in the sub-threshold regime. The idea was picked up for pacemakers and RFID tags, but never saw much acceptance beyond that.

After a lull that lasted a couple of decades, the topic regained some academic status in the late 1990s and early 2000s. By that time, the upcoming primacy of energy consumption was evident, and research started into ways that commercial circuit designers could reduce energy consumption. Sub-threshold design techniques were among those ideas.

It would be obvious to ask why, if this technology was developed in the 70s, it never caught on.

The answer to that question is, “Because it’s not so easy.” There is no fatal flaw, but the transition from super-threshold techniques has not been trivial.

Adapting the standard super-threshold flows and infrastructure for sub-threshold design presents numerous detailed challenges. These start with the very transistors themselves.

The output response of a transistor in the sub-threshold regime is subtle; detecting it requires great sensitivity. Currents change exponentially in response to changing voltages, but they’re exceedingly small currents.

Sub-threshold designs are also far more susceptible to process and environmental variation than are super-threshold designs. For example, the current in a slow process corner can be 10-100 times less than that for a nominal process. Given that the on/off current ratio (above) is only on the order of a thousand, this cannot be ignored.

Variations in temperature provide a good example of how environmental conditions create a challenge for the designer. Vth depends on temperature, and Ion depends exponentially on Vth

The development of Ambiq’s SPOT technology, which addresses all of these challenges, has been a multi-year effort involving multi-faceted solutions, starting with a better understanding of the transistors themselves.

A new solution from Keysight reduces system complexity and saves time for engineers designing and implementing high-power systems.

The N8900 Series prewired rack system for high-power DC applications is made up of 15 kW blocks that can deliver up to 90 kW and up to 3060 amps. Internal communications allow the system to operate as a single power supply and users can communicate via LAN, USB, or GPIB interfaces.

At electronica 2014, Bosch CEO Stefan Finkbeiner discussed the latest intelligent sensors and how they can be used in smartphones, IoT, and more.

Bosch’s BME280 sensor measures pressure, temperature, and humidity, which is useful for smartphones and buildings. And the tiny BMA355 accelerometer and the BMI160 low power IMU can find use in wearable devices.

The first 20 nanometers volumes reach the circuit is Intex Ultrascale KU040.

Source: http://www.etn.fi/index.php?option=com_content&view=article&id=2232:20-nanometrin-fpga-volyymituotantoon&catid=13&Itemid=101

There’s still a lot of life in Moore’s Law and a lot of smart people driving it forward and putting it to good use. That was my big takeaway from the 2014 International Electron Devices Meeting.

IEDM was a victory lap for Intel, which gave more details on the 14 nm finFET process it first described in September. IBM chomped at its heels, describing its own 14 nm finFET process optimized for its embedded DRAM.

Separately, TSMC gave a first, albeit somewhat limited, look at its improved 16 nm+ finFET process. Two of its customers — Avago and Renesas — gave the first public descriptions of prototype devices made in it.

Samsung presented eight papers but none that described its 14 nm process.

The event put to rest any doubt finFETs are the way forward for the bulk of the industry. STMicroelectronics was the lone voice advocating a planar silicon-on-insulator alternative.

Other than Samsung, no one else delivered papers on 3D NAND flash. All its competitors are probably working on it but are too close — or far away — to reveal their exact status.

Likewise, IEDM veterans thought they would have seen more papers on topics such as tunnel FETs and III-V materials that could be key for the 10 nm node and beyond. The lack of papers suggests rivals such as Intel, IBM, Samsung, and TSMC may be in the late stages of finding their secret recipes.

True three-dimensional (3-D) chips were demonstrated recently at the 2014 International Electron Devices Meeting (IEDM, Dec. 13-17, San Francisco) by Stanford University. Most 3-D chips use through-silicon-vias (TSVs) to stack separately manufactured dies, such as the Hybrid Memory Cube, which stacks DRAM die by Micron Technology, Inc., of Boise, Idaho.

A startup — BeSang Inc. of Beaverton, Ore. — has licensed its proprietary process to SK Hynix Inc. of Icheon, South Korea, for building true 3-D chips without TSVs. But Stanford’s demonstration showed that any fab can stack any number of layers of logic and memory atop a standard complementary metal oxide semiconductor (CMOS) die. For the demonstration, Stanford stacked a standard CMOS chip atop two layers of metal-oxide resistive random access memories (RRAM) and a top layer of logic circuitry using carbon-nanotubes as the transistor channel.

Managing sales and operations planning (S&OP) in a formalized way can put an electronics OEM at the head of the pack, and lead to a good year-end sales report. That’s the gift that keeps on giving during the holiday season.

Although accurate forecasting leads to myriad benefits, getting there can make even the most sophisticated organization feel less than merry. In fact, one in five organizations tags S&OP processes as the single most significant opportunity for improvement, according to research by E2Open.

variety of potential benefits for organizations focusing on S&OP, including:

Gross margin improvements of 25% to 35%
Significant savings from product and customer rationalization
Customer retention improvements of 10% or more
Order fulfillment rate improvements of 20% to 40%
Product introduction success rates growing in direct proportion to S&OP maturity