A startup founded by two teenagers is designing a parallel processor that it hopes delivers a 10x leap in performance per watt for high-end systems. Rex Computing will make open source its instruction set architecture in hopes of rallying supporters around it.

The startup’s ambitions are high, as explained by chief executive Thomas Sohmers, who recently became old enough to sign the company’s contracts. He aims to create an alternative to today’s processors and accelerators, which are too expensive (mainly in power consumption) to scale to the exaflop performance researchers hope to deliver in the next decade.

Sohmers was recently elected co-chairman of the high-performance working group under the Open Compute Project (OCP) started by Facebook. He hopes Rex can finish the design of its neo core as early as January and make it open source through the group.

The 3W Neo chip (above) packs into 80 mm2 256 cores, each consisting of a 64-bit ALU, IEEE floating point unit, and 128 Kbits of SRAM scratch pad memory. Each core has a 16 Gbyte/s link to its neighbors with about 384 Gbytes/s of aggregate bandwidth between chips.

Sohmers was inspired by Adapteva’s Epiphany chip, on which he based his first prototypes.

http://www.rexcomputing.com/

The Parallax Propeller is an interesting chip that doesn’t get a lot of love, but since the entire chip was released as open source, that might be about to change: people are putting this chip inside FPGA and modifying the binaries to give the chip functions that never existed in the original.

Last August, Parallax released the source for the P8X32A, giving anyone with an FPGA board the ability to try out the Prop for their own designs.

Parallax Propeller P8X32A-V With Addons
http://syso.name/s/parallax-propeller-p8x32a-v-with-64-i-o/

Open Sourcing something doesn’t actually acquire meaning until someone actually uses what has been unleashed in the wild. We’re happy to see a working example of Propeller 1 on an FPGA dev board.

You’ll remember that Parallax released the Propeller 1 as Verilog code a few weeks back. This project first loads the code onto the FPGA, then proves it works by running SIDcog, the Commodore 64 sound emulation program written in Spin for p8x32a processors.