There’s an old joke about how can you find the height of a building using a barometer. One of the punchlines is to drop the barometer from the roof and time how long it takes to hit the ground. We wonder if [Alexlao512] had that in mind when he wrote a post about unconventional uses of FPGAs. Granted, he isn’t dropping any of them off a roof, but still. The list takes advantage of things we usually try to avoid such as temperature variation, metastability, and the effects of propagation delays.

Unconventional uses of FPGAs
https://voltagedivide.com/2024/03/18/unconventional-uses-of-fpgas/

LILYGO’s T-FPGA Combines an Espressif ESP32-S3 with a Gowin GW1NSR FPGA on an M.2-Format Dev Board
Priced under $25, or a hair under $30 with carrier board, the M.2 T-FPGA is a compact entry point for low-power FPGA experiments.
https://www.hackster.io/news/lilygo-s-t-fpga-combines-an-espressif-esp32-s3-with-a-gowin-gw1nsr-fpga-on-an-m-2-format-dev-board-47fc1e5b1702

A neat open source project, Vidbo is a web server that facilitates graphical interface HDL simulations for FPGA development.

Most FPGA developers/engineers will agree that one of the headaches of designing is getting a good simulation set up to prove in the HDL design’s functionality. Pretty much all of the IDEs for the FPGA chips out there (Vivado, Libero, etc.) have built-in simulators, but they don’t always provide an intuitive view of what’s going on. Olof Kindgren saw this gap in the market and addressed it with his latest open source project, Vidbo.

Vidbo, short for virtual board, is a web server with a graphical interface with a protocol created to communicate with a simulated FPGA development board or chip via web sockets.

Vidbo is the marriage of two previous projects of virtual development boards for HDL design and Verilatio which was the first revision of the web socket communication protocol with the HDL simulator.

The example project in the main Vidbo repository simulates a Nexys A7 board from Digilent with Verilog and C++ that implements the backend functionality of each component and HTML/SVG that comprises the front end web browser GUI

https://github.com/olofk/vidbo

65F02 Is a 100 MHz Drop-In Replacement for Vintage 8-Bit Computers
FPGA on a 40-pin package boosts performance on the C64 and Apple II.
https://www.hackster.io/news/65f02-is-a-100-mhz-drop-in-replacement-for-vintage-8-bit-computers-ef667b0ebed3

Microprocessors like the 8-bit 6502 from MOS Technologies were at their height of popularity during the 1980s and 1990s. A modern variant of the original design is still available today that runs up 14 MHz. However, Jürgen Müller’s latest project advances that number by an order of magnitude. The 65F02 is a 6502 pin and instruction compatible processor replacement that runs at 100 MHz!

65F02′s 40-pin DIP compatible PCB fits directly into a socket designed for a 40-pin IC. The top side has the Spartan-6 FPGA, Flash Memory, configuration switches, and an LED. The bottom side of the board contains decoupling capacitors, regulators, and logic level shifters.

The part number “65F02″ fits nicely into the 6502′s lineage. When MOS Technology first developed the 6502, it licensed the design to other chip manufacturers. Some of those had process variants. Later, the 65c02 emerged, which was a CMOS version. That particular style is still available today from Western Design Center (WDC), the last remnants of the original MOS company. That chip, however, “only” runs up to 14 MHz. Somewhat slow compared to today’s clock speeds, but blazing fast to the original 2 MHz limit.

Internally the 65F02 runs at 100 MHz. However, external bus access operates slower to accommodate system buses that are not ready for 40 years of computing advancements. In addition, 65F02 mirrors external video memory to internal fast RAM to make video operations faster.

Addressing RAM on older systems did present a challenge. The original 6502 had a 16-bit address bus, which means it could only access 64 kilobytes of memory space. As a result, most computers implemented bank switching to address more memory. However, each computer design took a different approach.

Müller made all of 65F02′s design files available. For the schematic and PCB, there are Eagle files. You need Xilinx WebISE 14.7 if you want to modify the FPGA code. And to program the FPGA, Müller used the same programming hardware used in the TinyFPGA project.

http://www.e-basteln.de/computing/65f02/65f02/

At its heart is a dev board containing an Intel Cyclone SoC/FPGA, to which a USB hub must be added, and then a memory upgrade to run all but the simplest of cores. Once the hardware has been taken care of it almost seems as though there are no classic platforms for which there isn’t a core, as a quick browse of the MiSTer forum attests. We are treated to seamless switching between SNES and NED platforms, and even switching different SID chip versions during a running Commodore 64 demo.