Nvidia CEO Jensen Huang has become the first head of a major semiconductor company to say what academics have been suggesting for some time: Moore’s Law is dead.

The enablers of an architectural advance every generation — increasing the size of pipelines, using superscalar tweaks and speculative execution — are among the techniques that are now lagging in the effort to keep pace with the expected 50 percent increase in transistor density each year, Huang told a gathering of reporters and analysts at the Computex show in Taipei.

“Microprocessors no longer scale at the level of performance they used to — the end of what you would call Moore’s Law,” Huang said. “Semiconductor physics prevents us from taking Dennard scaling any further.”

Dennard scaling, also known as MOSFET scaling, is based on a 1974 paper co-authored by Robert H. Dennard, after whom it is named. Originally formulated for MOSFETs, it states, roughly, that as transistors get smaller their power density stays constant, so that power use stays in proportion with area.

The diminishing returns from Moore’s Law and Dennard scaling have seen the semiconductor industry enter a mature stage in which just a handful of chipmakers can afford the multibillion dollar investments required to push the process technology forward. By now, only a few chip designers have the deep pockets to double down on fabricating silicon at the 16nm and 14nm nodes, design rules where the distinction has become increasingly blurred.

That stagnation in the progress of technology has also led to rapid industry consolidation in recent years that’s resulted in a flurry of multi-billion dollar mergers and acquisitions.

Part 2: Heterogeneity and architectures become focus as scaling benefits shrink; IP availability may be problematic.

The ability to shrink devices will continue for at least four more nodes as EUV begins to ramp, but it’s just one of a growing number of options.

Moore’s Law has been synonymous with “smaller, faster, cheaper” for the past 52 years, but increasingly it is viewed as just one of a number of options—some competing, some complementary—as the chip industry begins zeroing in on specific market needs.

This does not make Moore’s Law any less relevant. The number of companies racing from 16/14nm to 7nm is higher than the initial rush to finFETs at 16/14nm, according to numerous industry sources. But that migration also needs to be put in perspective:

• Node naming became meaningless after 20nm, when foundries leveraged the same back-end of line measurements using 16/14nm finFETs. Consequently, there is no agreed upon definition for what is 10nm or 7nm. A more useful number is a comparison of performance and power by individual foundries.

• Even the strongest proponents of Moore’s Law are slowing from one node ever two years to a node every three or four years. But industry sources say a number of companies plan to skip nodes due to rising cost and complexity, so rather than turn out a production chip at every node

• Big systems companies, such as Apple and Google, are developing chips that defy standard measurements because they are application-specific and heterogeneous. In comparison, most node-specific measurements are based on ASICs, not ASSPs.

As a result, how much of the semiconductor industry is truly following Moore’s Law is no longer a straightforward exercise in counting. Logic devices are still shrinking, but not at consistent or comparable rates.

“For the past 50 years, the cheapest and easiest way to increase complexity was to shrink the feature size and grow the wafer diameter,” said Wally Rhines, chairman and CEO of Mentor, a Siemens Business. “It’s not the easiest way anymore. There is a tradeoff. We will do the things that are most economic for the capabilities we want.”

Lithography
Ever since double patterning became a requirement on the critical metal layers—namely metal 1 and metal 2 at 20nm—most experts assumed that the primary limiting factor for device shrinking would be lithography.

Fortunately, though, chipmakers have been able to extend traditional optical lithography. Using various multiple patterning schemes, chipmakers are able to split the mask and pattern each one separately. In doing so, they can extend today’s 193nm wavelength lithography to 16nm/14nm, 10nm, and even 7nm.

But at 7nm or 5nm, the pattern complexity and mask counts are becoming limiting factors for immersion/multi-patterning. A 28nm device has 40 to 50 mask layers. In comparison, a 14nm/10nm device has 60 layers, with 7nm expected to jump to 80 to 85. At 5nm, there could be 100 layers.

To simplify the flow at 7nm and/or 5nm, chipmakers have been waiting for extreme ultraviolet (EUV) lithography, a 13.5nm wavelength technology. EUV was expected at 45nm, but ran into a number of issues that only recently have been resolved.

Conclusion
Tying this all back into Moore’s Law may or may not make sense. The original observation was fairly straightforward, but it has been reinterpreted so many times that it’s hard to say what is or isn’t Moore’s Law anymore.

Sophie Wilson, designer of the original Acorn Micro-Computer in the 1970s and later developer of the instruction set for ARM’s low-power processors that have come to dominate the mobile device world has such thoughts. And when Wilson talks about processors and the processor industry, people listen.

Wilson’s message is essentially that Moore’s Law, which has been the driving force behind chip development in particular and the computer industry as a whole for five decades, has hit its limits, and that despite the best efforts by chip designers around the world, the staggering gains in processor performance over that time will not be seen again.

Is Moore’s Law dead? Brigadier General Paul Fredenburgh, commandant of the Dwight D. Eisenhower School for National Security and Resource Strategy, asked that question to four industry CEOs last week while visiting Silicon Valley with some of his students. He received four highly nuanced, if not different, answers.

From one perspective or another, all of the CEOs were all correct. It’s taking longer to move from one process node to the next, but there is significantly more compute power being offered at each new node. While that isn’t technically a doubling of transistors every two years or so, performance continues to increase an average of 30% every couple of years, either through architectural changes, new materials or different packaging approaches.

Moreover, there is no end in sight to how long this will continue. 2.5D, fan-out wafer-level packaging and full 3D will radically improve performance and lower power.

What is becoming obvious, though, is that Moore’s Law as it was originally written is getting tougher to follow. There are several reasons for this:

1. Quality is becoming a bigger issue as semiconductors begin making inroads in safety-critical and industrial markets, including autonomous vehicles, robotics and personalized medicine.

2. Market demand for moving to the next process node will continue, but the number of high-volume markets is shrinking. Companies such as Samsung, Intel and Xilinx all need increased transistor density. But for other companies, density isn’t the only way to solve their power/performance/cost issues.

3. Despite the fact that EUV is moving forward after years of delays, the big challenge with advanced nodes is time. EUV will help. But that’s only one piece of the puzzle. It takes longer to design chips at advanced nodes

While Moore’s Law is continuing in one way, it also has ended in another. And while collectively this is referred to as Moore’s Law, it bears only glimmers of resemblance to the observation first penned by Gordon Moore.

Nicky Lu, executive director of the Taiwan Semiconductor Industry Association, is looking forward to the coming era of a “virtual” Moore’s Law, leading to a resumption of growth and profitability in the chip industry.

“There will be another 30 years of growth for the semiconductor industry,” Lu predicted in an interview with EE Times. “We are going to see ‘effective’ 1nm. Moore’s Law will become a ‘virtual’ Moore’s Law.

There is evidence that linear scaling has already reached its physical limits. “People say they are doing 10nm process modes, but you will not find any line widths at that level,” Lu says.

Departing Flatland
That’s why technology development has gone non-linear. In 2011, Intel announced its Tri-gate technology, leading the way from planar development of transistors on silicon into three dimensions. With 3D, even scaling by a factor of 0.85 results in a transistor density that is more like 0.5 scaling in two dimensions, Lu says.

Other companies have followed that trend. Toshiba built 3D NAND in 48 layers, and that memory has been used in Apple’s iPhone 7. Samsung has taken the idea a step further with the creation of a 64-layer flash memory device. The technology level was only 32nm, yet it was the virtual equivalent of 13nm, Lu notes.

The industry is at a crossroads: some designs pursue scaling to 7nm while the majority stay on 28nm or older nodes.

As we have predicted more than two years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

Our 2014 blog 28nm — The Last Node of Moore’s Law has now been confirmed. At the time we wrote: “After the 28nm node, we can continue to make transistors smaller, but not cheaper.” It is illustrated in the following slide, presented by Samsung at the recent Semicon West 2016.