<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	
	>
<channel>
	<title>Comments on: New Armv9 CPU core</title>
	<atom:link href="http://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/feed/" rel="self" type="application/rss+xml" />
	<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/</link>
	<description>All about electronics and circuit design</description>
	<lastBuildDate>Wed, 22 Apr 2026 04:56:12 +0000</lastBuildDate>
		<sy:updatePeriod>hourly</sy:updatePeriod>
		<sy:updateFrequency>1</sy:updateFrequency>
	<generator>http://wordpress.org/?v=3.9.14</generator>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1753013</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 27 Jan 2022 19:32:59 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1753013</guid>
		<description><![CDATA[New ARM processor featuring CHERI architecture - 

&quot;Several years ago, researchers at the University of Cambridge, in collaboration with Arm, developed an experimental architecture called [CHERI—capability hardware-enhanced RISC instructions](https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/)—which uses 64-bit Armv8-A to address memory safety, particularly in programming languages.&quot;

Arm Puts Security Architecture to the Test With New SoC and Demonstrator Board
https://www.allaboutcircuits.com/news/arm-puts-security-architecture-to-test-with-new-soc-and-demonstrator-board/]]></description>
		<content:encoded><![CDATA[<p>New ARM processor featuring CHERI architecture &#8211; </p>
<p>&#8220;Several years ago, researchers at the University of Cambridge, in collaboration with Arm, developed an experimental architecture called [CHERI—capability hardware-enhanced RISC instructions](<a href="https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/" rel="nofollow">https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/</a>)—which uses 64-bit Armv8-A to address memory safety, particularly in programming languages.&#8221;</p>
<p>Arm Puts Security Architecture to the Test With New SoC and Demonstrator Board<br />
<a href="https://www.allaboutcircuits.com/news/arm-puts-security-architecture-to-test-with-new-soc-and-demonstrator-board/" rel="nofollow">https://www.allaboutcircuits.com/news/arm-puts-security-architecture-to-test-with-new-soc-and-demonstrator-board/</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718419</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 19:47:06 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718419</guid>
		<description><![CDATA[https://developer.arm.com/architectures/architecture-security-features]]></description>
		<content:encoded><![CDATA[<p><a href="https://developer.arm.com/architectures/architecture-security-features" rel="nofollow">https://developer.arm.com/architectures/architecture-security-features</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718418</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 19:46:51 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718418</guid>
		<description><![CDATA[https://developer.arm.com/architectures/cpu-architecture/a-profile?_ga=2.122826188.612523548.1625680844-1406347065.1625592626]]></description>
		<content:encoded><![CDATA[<p><a href="https://developer.arm.com/architectures/cpu-architecture/a-profile?_ga=2.122826188.612523548.1625680844-1406347065.1625592626" rel="nofollow">https://developer.arm.com/architectures/cpu-architecture/a-profile?_ga=2.122826188.612523548.1625680844-1406347065.1625592626</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718417</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 19:46:11 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718417</guid>
		<description><![CDATA[https://source.android.com/devices/tech/debug/tagged-pointers]]></description>
		<content:encoded><![CDATA[<p><a href="https://source.android.com/devices/tech/debug/tagged-pointers" rel="nofollow">https://source.android.com/devices/tech/debug/tagged-pointers</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718416</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 19:45:45 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718416</guid>
		<description><![CDATA[https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/enhancing-memory-safety]]></description>
		<content:encoded><![CDATA[<p><a href="https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/enhancing-memory-safety" rel="nofollow">https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/enhancing-memory-safety</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718415</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 19:45:19 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718415</guid>
		<description><![CDATA[https://www.arm.com/why-arm/architecture/cpu]]></description>
		<content:encoded><![CDATA[<p><a href="https://www.arm.com/why-arm/architecture/cpu" rel="nofollow">https://www.arm.com/why-arm/architecture/cpu</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718403</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 14:47:02 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718403</guid>
		<description><![CDATA[https://www.arm.com/campaigns/arm-vision]]></description>
		<content:encoded><![CDATA[<p><a href="https://www.arm.com/campaigns/arm-vision" rel="nofollow">https://www.arm.com/campaigns/arm-vision</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718402</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 14:46:32 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718402</guid>
		<description><![CDATA[compiler support for SVE2 for GCC and LLVM.]]></description>
		<content:encoded><![CDATA[<p>compiler support for SVE2 for GCC and LLVM.</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718401</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 14:46:04 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718401</guid>
		<description><![CDATA[https://armkeil.blob.core.windows.net/developer/Files/pdf/graphics-and-multimedia/confidential-computing-pulse-survey.pdf]]></description>
		<content:encoded><![CDATA[<p><a href="https://armkeil.blob.core.windows.net/developer/Files/pdf/graphics-and-multimedia/confidential-computing-pulse-survey.pdf" rel="nofollow">https://armkeil.blob.core.windows.net/developer/Files/pdf/graphics-and-multimedia/confidential-computing-pulse-survey.pdf</a></p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Tomi Engdahl</title>
		<link>https://www.epanorama.net/blog/2021/03/31/new-armv9-cpu-core/comment-page-1/#comment-1718400</link>
		<dc:creator><![CDATA[Tomi Engdahl]]></dc:creator>
		<pubDate>Thu, 08 Jul 2021 14:45:16 +0000</pubDate>
		<guid isPermaLink="false">https://www.epanorama.net/blog/?p=188175#comment-1718400</guid>
		<description><![CDATA[https://www.arm.com/blogs/blueprint/armv9]]></description>
		<content:encoded><![CDATA[<p><a href="https://www.arm.com/blogs/blueprint/armv9" rel="nofollow">https://www.arm.com/blogs/blueprint/armv9</a></p>
]]></content:encoded>
	</item>
</channel>
</rss>
