Digital Electronics Page
An understanding of the technology that provides the basis for the construction of computers is an important component of knowledge for everybody working with electronics and computers. underlying principles of the application of this technology are electrical circuits and Boolean algebra. These principles have been used with a number of different technology-types over the past 40 years to produce computers and other digital electronics.
In 1947, an enormous stride was taken in electrical technology with the advent of the transistor(short for transfer-resistance). The success of the transistor and advances in solid state physics provided the foundation for another new technology, integrated circuits, IC's.
The first integrated circuits were produced by scientists at Texas Instruments, and Fairchild Camera and Instrument Company, in 1959. These were circuits on single chips with up to ten components on them, small scale integration (SSI). Since that time the number of components on IC's, integrated circuits, has approximately doubled every year. In 1965 IC's with up to 100 gates, medium scale integration (MSI), were being produced. In 1971 large scale integration (LSI) was used to put thousands of gates on a chip. Currently major IC manufacturers are using very large scale integration, VLSI, to pack hundreds-of-thousands or millions of components on a single chip.
The fabrication of common integrated circuits is based on the structuring of N-type and P-type semiconductors with a conducting material, sometimes aluminum, and an insulating silicon material. The manner in which these materials are put together determines the characteristics and function of the IC's.
There are several different families of logic gates. Each family has its capabilities and limitations, its advantages and disadvantages.
Bipolar or conventional transistors are used in manufacturing TTL (transistor-transistor logic) and ECL (emitter-coupled logic) devices. Field effect transistors or unipolar transistors are used to manufacture PMOS (P-type metal-oxide semiconductor), NMOS (N-type metal-oxide semiconductor) and CMOS (complementary metal-oxide semiconductor) devices. Each of these logic families, TTL, ECL, PMOS, NMOS and CMOS, has a specific set of characteristics that make it desirable for certain applications.
Each logic family has a basic gate from which all devices are built. The TTL family uses the NAND gate, the ECL family uses the NOR gate and the CMOS family uses the inverter. The differences between the families are usually analyzed by looking at the characteristics of the basic gate associated with the family.
The four basic characteristics evaluated are:
- Power dissipation: Power consumed by the gate when it operates. This power needs to be supplied by the power supply.
- Propagation delay: The term propagation-delay refers to the average time it takes the input signal to propagate to the output. So this term indicates the speed of the logic gate operation.
- Fan-out: The output of a gate is usually connected to one or a number of other devices' inputs. The amount of current supplied from the output of a gate is limited, therefore the output of a gate can only be connected to a limited number of inputs. Fan-out refers to the number of standard loads (inputs) that the output of a gate can be connected to without impairing its normal operation.
- Noise margin: Noise margin refers to the maximum noise voltage that can be added to the generated signal in a digital circuit before an undesirable change is caused in the circuit output.
Most logic families share a common characteristic: their inputs require a certain amount of current in order to operate correctly. CMOS gates work a bit differently, but still represent a capacitance that must be charged or discharged when the input changes state. The current required to drive any input must come from the output supplying the logic signal. Therefore, we need to know how much current an input requires, and how much current an output can reliably supply, in order to determine how many inputs may be connected to a single output. Rather than working constantly with actual currents, we determine the amount of current required to drive one standard input, and designate that as a standard load on any output. Now we can define the number of standard loads a given output can drive, and identify it that way. Fan-out tells the number of standard loads that can be reliably driven by an output, without causing the output voltage to shift out of its legal range of values.
In digital circuitry a circuit which recognizes a high level to be a logical-1 (true) and a low level as a logical-0 (false) is said to use positive logic. A circuit which uses a low level to represent logical-1 and a high level to represent logical-0 is said to use negative logic.
Within each family there is a range of voltages that the circuit will recognize as a high or low level.
- Logic Threshold Levels Rate this link
- Introduction to digital electronics Rate this link
- Inside Logic Gates - This document series introduces you to Diode Logic (DL), Resistor-Transistor Logic (RTL), Diode-Transistor Logic (DTL), Transistor-Transistor Logic (TTL), Emitter-Coupled Logic (ECL) and CMOS logic families. Rate this link
Logic circuts from discrete components
Diode logic gates use diodes to perform AND and OR logic functions. Diodes have the property of easily passing an electrical current in one direction, but not the other. Thus, diodes can act as a logical switch.
Diode logic gates are very simple and inexpensive, and can be used effectively in specific situations. However, they cannot be used extensively, as they tend to degrade digital signals rapidly. However, they do work for one stage at a time, if the signal is re-amplified between gates. In addition, they cannot perform a NOT function, so their usefulness is quite limited.
Resistor Transistor Logic (RTL)
Resistor-transistor logic gates use Transistors to combine multiple input signals, which also amplify and invert the resulting combined signal. Often an additional transistor is included to re-invert the output signal. This combination provides clean output signals and either inversion or non-inversion as needed.
RTL gates are almost as simple as DL gates, and remain inexpensive. They also are handy because both normal and inverted signals are often available. However, they do draw a significant amount of current from the power supply for each gate. Another limitation is that RTL gates cannot switch at the high speeds used by today's computers, although they are still useful in slower applications.
RTL is a relatively old technology. It has been used in circuit built form discrete components and in some very early logic ICs. Although they are not designed for linear operation, RTL integrated circuits have been sometimes used as inexpensive small-signal amplifiers, or as interface devices between linear and digital circuits. RTL logic ICs are no longer commercially available. If you need some RTL logic nowadays, you need to build it from discrete components.
Diode-Transistor Logic combines the diode logic with transistor based logic level amplifier. By letting diodes perform the logical AND or OR function and then amplifying the result with a transistor, we can avoid some of the limitations of RTL. DTL takes diode logic gates and adds a transistor to the output, in order to provide logic inversion and to restore the signal to full logic levels.
The advantage of this circuit over its RTL equivalent is that the OR logic is performed by the diodes, not by resistors. Therefore there is no interaction between different inputs, and any number of diodes may be used. A disadvantage of this circuit is the input resistor to the transistor. Its presence tends to slow the circuit down, thus limiting the speed at which the transistor is able to switch states.
CMOS is very popular digital IC family. Its low power consumption and high fan-out make it a desirable choice when designing a circuit. CMOS's primary disadvantage is that it cannot be packed as densely as TTL or NMOS, this is due to the fact that each transistor in a CMOS circuit is actually made from a PMOS transistor and an NMOS transistor.
In CMOS (Complementary Metal-Oxide Semiconductor) technology, both N-type and P-type transistors are used to realize logic functions. Today, CMOS technology is the dominant semiconductor technology for microprocessors, memories and application specific integrated circuits (ASICs). The main advantage of CMOS over NMOS and bipolar technology is the much smaller power dissipation. Unlike NMOS or bipolar circuits, a CMOS circuit has almost no static power dissipation. Power is only dissipated in case the circuit actually switches. This allows to integrate many more CMOS gates on an IC than in NMOS or bipolar technology, resulting in much better performance.
The fundamental building blocks of CMOS circuits are P-type and N-type MOSFET transistors. The two MOSFETs are designed to have matching characteristics. Thus, they are complementary to each other. When off, their resistance is effectively infinite; when on, their channel resistance is about 200 ohms. Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting.
Typical power dissipation of CMOS is 0.1 mW per gate. The propagation delay is typically 25 ns. Noise margin is 3.0 V. Typical fan-out is 50. CMOS logic is normally powered by 5..12V power source. CMOS logic typically accepts 3-16V DC power source.
The logic level on CMOS logic depend on the operating voltage. The voltage limits for Vin high and Vin low are percentages of the supply voltages. The range for Vin low is from ground to 30% of the supply voltage. The range for Vin high is normally from 70% of supply voltage to the supply voltage.
For CMOS logic operating with 5V power source the logic voltage levels are typically following:
OUTPUT LOGIC 1: around 4.5-5V LOGIC 0: around 0-0.5V INPUT LOGIC 1: 3.5-5V LOGIC 0: 0-1V
CMOS has some unique components. One type of gate that is unique to CMOS technology is the bilateral switch, or transmission gate. It makes full use of the fact that the individual FETs in a CMOS IC are constructed to be symmetrical. That is, the drain and source connections to any individual transistor can be interchanged without affecting the performance of either the transistor itself or the circuit as a whole. The bilateral siwtch can nicely switch digital and analogue signals on both directions through the gate.
Well-known CMOS logic families:
4000 True CMOS (CMOS levels) 74C CMOS implementation oc 74xx series 74HC High speed - CMOS (CMOS levels) 74HCU High speed - CMOS (Unbuffered output CMOS levels) 74HCT High speed - CMOS - TTL inputs 74AHC Advanced - High speed - CMOS 74AHCT Advanced - High speed - CMOS - TTL inputs 74FCT Fast - CMOS - TTL inputs (speed variations) 74AC Advanced - CMOS 74ACT Advanced - CMOS - TTL inputs 74ACQ Advanced - CMOS - Quiet outputs 74ACTQ Advanced - CMOS - TTL inputs - Quiet outputs 74ALB Advanced - Low Voltage - BiCMOS
There is one unfortunate effect that can happen with many CMOS components: latch-up. SCR latch-up is a parasitic phenomena that has existed in circuits fabricated using bulk silicon CMOS technologies. The latch-up mechanism, once triggered, turns on a parasitic SCR internal to CMOS circuits which essentially shorts VCC to ground. This generally destroys the CMOS IC or at the very least causes the system to malfunction. In order to make MM54HC/MM74HC high speed CMOS logic easy to use and reliable it is very important to eliminate latch-up. Latch-up used to be a large problem eariler, but it has reduced during years when components have became better, but still today you should acknowledge it.
Latch-up most commonly can be turned on by by applying a voltage greater than Vcc or less than ground any input or output, which forward biases the input or output diodes. These diodes can act as the gate to the parasitic SCR. Parasitic SCR structures can result due to the fabrication of CMOS input protection circuitry. Typically there is a distributed diode connected to VDD and another diode to VSS. The diodes are connected together at the input node. Typically there is also a series resistor primary intended for static protection, but also provides latch-up protection. An SCR structure results when the VDD referenced diode is fabricated in close proximity to an N-channel transistor or when the Vss referenced diode is located close to a P-channel device. In normal operation the parasitic SCR structure does not cause problems, but if too hugh current gets fed to the IC through those diodes, the latch-up can occur. The actual current calues needed to cause the latch-up are much greater than the 0.3V and 10mA limits typically on the data sheets. Typically it requires voltages from 1.0V to 1.9V and currents from 90mA to 200mA to trigger output latch-up.
Most modern CMOS chips include two protection diodes at every I/O pad, wired as clamps. These diodes limit the input voltage from going much higher than VCC or lower than ground. This limitation on the input voltage prevents gate-oxide blowout or latch-up of the entire chip, either of which might otherwise easily occur on an unprotected I/O pad during an ESD transient. Beware that no standards exist that govern the implementation of ESD diodes in CMOS chips. Implementations vary widely.
- Understanding Latch-Up in CMOS Applications - Latch-up has long been a bane to CMOS IC applications; its occurrence and theory have been the subjects of numerous studies and articles. The applications engineer and systems designer, however, are not so much concerned with the theory and modeling of latch-up as they are with the consequences of latch-up and what has been done by the device designer and process engineer to render ICs resistant to latch-up. Rate this link
- Understanding Buffered and Unbuffered CD4xxxB Series Device Characteristics - Many CMOS suppliers have concentrated on promoting buffered B-series products, with applications literature focusing on the attributes and use of the buffered types. This practice has left an imbalance in the understanding and application of both buffered and unbuffered gates. In some instances, customers are not using unbuffered products when they are the best choice for the intended application. This application report offers clarification of the relative merits of the buffered and unbuffered CMOS devices. Rate this link
- Fairchild.s Process Enhancements Eliminate the CMOS SCR Latch-Up Problem In 74HC Logic Rate this link
- Logic levels for CMOS ICs - CMOS ICs can operate on supply voltages up to 16 Volts. The voltage limits for Vin high and Vin low are percentages of the supply voltages. Rate this link
- 4000B Series CMOS Functional Diagrams Rate this link
- CMOS Logic Rate this link
- CMOS logic introduction Rate this link
ECL (emitter coupled logic) is used for circuits which will operate in a high speed environment. ECL offers the lowest propagation delay of all the logic families. ECL is a non-saturating form of digital bipolar circuit architecture. It is the fastest bipolar circuit architecture available today. ECL logic can drive heavy capacitive loads or controlled-impedance transmission lines without significant effect on switching speed.
As clock speeds rise beyond 100 MHz, the advantages of using ECL become more obvious. Most of these advantages involve the use of differential signal transmission and controlled impedance transmission lines with proper termination. ECL is designed with termination resistors that allow high-frequency signals to propagate with minimal overshoot and reflection. Differential signals are less susceptible to ground noise problems, as all noise becomes common-mode.
General data for 10k ECL series: Typical power dissipation of ECL is 25 mW per gate. The propagation delay is typically 0.5-2 ns. Noise margin is 0.2 V. Typical fan-out is 25. ECL logic is normally powered by -5..-5.2V power source (for 10k series). The power source for 100k series is -4.5V.
Typical logic levels on ECL system are -0.95..-0.7V for logic high and -1.9..-1.6V for logic low.
General data for 100k ECL series: Reduced power-supply voltage, VEE = -4.5 V. Somewhat different logic levels than 10k series, as a consequence of the different supply voltage. Shorter propagation delays, typically 0.75 ns. Shorter transition times, typically 0.70 ns. Higher power consumption, typically 40 mW per gate.
Know ECL device famielies (nanoseconds tell rise and fall times):
MEC I 8nS MEC II 2nS MEC III (16XX) 1nS 101xx 100 series 10K ECL, 3.5nS 102xx 200 series 10K ECL, 2.5nS 108xx 800 series 10K ECL, voltage compensated, 3.5nS 10Hxxx 10K - High speed, voltage compensated, 1.8nS 10Exxx 10K - ECLinPS, voltage compensated, 800pS 100xxx 100K, temperature compensated 100Hxxx 100K - High speed, temperature compensated 100Exxx 100K - ECLinPS, temp, voltage comp., 800pS
A standard Emitter Coupled Logic (ECL) output driver typically uses a current switching differential with an emitter follower for level shifting the output. This output driver architecture presents about 6 - 8 ohms internal impedance in both 800 mV swinging around a DC voltage point of VCC - 1.3 V when properly terminated and operating correctly. When properly terminated, the outputs will generate both: static state voltage levels VOL (LOW) or VOH (HIGH) and a dynamic transition edge (tr or tf) between state.
Left open, an output will only swing a few millivolts due to parasitic .minimum current. leakage paths. Shorted to VEE, a maximum current will develop, limited only by the output transistor 8 impedance, and may cause damage to the output. Worst case short circuit current risks destruction of the devices.
ELC connections generally use 50 ohm coaxial cable and the terminations are matched to this. The line is generally terminated at the line receiving end. In some cases series damping termination technisques could be used.
In cases where differential ECL signals are used, a pair of differential ECL level signal carry the data. In those cases the signal is generally carried through a pair of 50 ohm coaxial cables or a 100 ohms twisted pair wire. Differential ECL outputs can be terminated as independent complimentary single ended lines.
- Termination of ECL Logic Devices Rate this link
- Emitter Coupled Logic - This is a general introduction to ECL technology. Rate this link
- ECL Outputs - This application note covers the principal advantages of using ECL outputs and makes recommendations concerning layout and wiring methods for parts such as the ICD2062. Rate this link
- ECL Design Principles Rate this link
PECL (positive-referenced emitter-coupled logic) is a special version of ECL powered by +5V power source (same as used by most TTL and CMOS ICs). PECL originates from ECL but uses a positive power supply. The relatively small swing of the PECL signal makes this logic suitable for high-speed serial and parallel data links. First developed by Motorola, the PECL standard has long since gained popularity with the rest of the electronics industry.
It is auite common in telecom ICs to provide differential PECL-compatible inputs and outputs on CMOS devices, allowing a direct interface between the CMOS device and a device such as a fiber-optic transceiver that expects ECL or PECL levels. In fact, as CMOS circuits have migrated to 3.3-V power supplies, it has even been possible to build PECL-like differential inputs and outputs that are simple referenced to the 3.3-V supply instead of a 5-V supply.
Note on relation of ECL and PECL: Positive ECL (PECL, pronounced .peckle.) uses a standard +5.0-V power supply. Note that there.s nothing in the ECL 10K circuit design that requires VCC to be grounded and VEE to be connected to a -5.2-V supply. The circuit will function exactly the same with VEE connected to ground, and VCC to a +5.2-V supply. Thus, PECL components are nothing more than standard ECL components with VEE connected to ground and VCC to a +5.0-V supply. The voltage between VEE and VCC is a little less than with standard 10K ECL and more than with standard 100K ECL, but the 10H-series and 100K parts are voltage compensated, designed to still work well with the supply voltage being a little high or low.
Like ECL logic levels, PECL levels are referenced to VCC, so the PECL HIGH level is about VCC - 0.9 V, and LOW is about VCC - 1.7 V, or about 4.1 V and 3.3 V with a nominal 5-V VCC. Since these levels are referenced to VCC, they move up and down with any variations in VCC.
A typical PECL interface output consists of a differential pair that drives a pair of emitter followers opearting in active region, with DC current flowing all the times. The proper termination for a PECL output is 50 ohms to voltage VCC-2V. At this termination, both OUT+ and OUT- will typically be VCC-1.3V, resulting in a DC current flow of approximately 14mA. The PECL output impedance is low, typically on the order of 4-5 ohms which provides superior driving capability.
The PECL interface is suitable for both +5.0V and +3.3V power supplies. When the power supply is +3.3V, it is commonly referred to as low-voltage PECL (LVPECL).
Careful attention must be paid to power-supply decoupling in order to keep the power-supply rail noise free. Also, the AC and DC requirements of the PECL outputs place additional constraints on termination networks.
Hot swapping presents a potential risk to an unpowered or powered down Positive mode ECL device inputs driven by a typical PECL level signal. When a receiver VCC is off or powered down, the VCC Power Supply typically appears as a low impedance source at 0.0 V capable of sinking considerable current. Typical PECL input signal levels present positive voltages that forward bias the input ESD protection diode structure and the input base collector junction. Potentially lethal current paths may develop through forwarded junctions to VCC.
In many applications where different ECL families needs to be interconnected receiver inputs may be level shifted using capacitive coupling and adjusting VBIAS within the acceptable common mode range.
- Termination of ECL Logic Devices Rate this link
- PECL and ECL 100k Introduction - This is a sample chapet from Digital Design Principles and Practices book. Rate this link
- Introduction to LVDS, PECL, and CML Rate this link
- ECL Outputs - This application note covers the principal advantages of using ECL outputs and makes recommendations concerning layout and wiring methods for parts such as the ICD2062. Rate this link
TTL and related logic systems
The TTL family's characteristics have made it the most popular logic family industry. Although, it does not stand out in any one area its speed and reliability have made it popular.
- Logic low: 0-0.4V
- Logic high: 2.4-5V
Standard 5V TTL
Standard TTL level ICs work on approximate the following voltage levels:
OUTPUT: LOGIC 1: 2.7-5V LOGIC 0: 0-0.4V INPUT: LOGIC 1: 2-5V LOGIC 0: 0-0.8V
Typical power dissipation of standard TTL is 10 mW per gate. The propagation delay is typically 10 ns. Noise margin is 0.4 V. Typical fan-out is 10.
In TTL family there are also some ICs with open collector outputs.
5V TTL logic families and related families:
74xx True TTL 74L Low power 74S Schottky 74H High speed TTL 74LS Low power - Schottky 74AS Advanced - Schottky 74ALS Advanced - Low power - Schottky 74F Fast TTL 74FAST Fast - Advanced - Schottky 74C CMOS 74HC High speed - CMOS 74HCU High speed - CMOS (Unbuffered output) 74HCT High speed - CMOS - TTL inputs 74AHC Advanced - High speed - CMOS 74AHCT Advanced - High speed - CMOS - TTL inputs 74FCT Fast - CMOS - TTL inputs (speed variations) 74AC Advanced - CMOS 74ACT Advanced - CMOS - TTL inputs 74FACT Advanced - CMOS - TTL inputs 74ACQ Advanced - CMOS - Quiet outputs 74ACTQ Advanced - CMOS - TTL inputs - Quiet outputs
- 74xx/54xx Family TTL Circuits - nice drawings of the most commonly used chips from 74xx series Rate this link
- Specifications for various 74xx Chips Rate this link
- An Introduction to and Comparison of 54HCT/74HCT TTL Compatible CMOS Logic - National Semiconductor Application Note 368 Rate this link
TTL compatible CMOS logic
Low voltage TTL (3V and 3.3V)
Operating voltages for digital systems have dropped from 5 V to 3 V or lower, because of the demand for higher-speed logic families that use ICs with smaller geometries. Contributing to the drop as well are the low power-consumption requirements of mobile wireless devices, such as cellular phones, handheld computers, and GPS receivers.
Today, there are many 3-V logic families available. (Note that the term 3 V is commonly used when the supply voltage is 3.3 V).
Typical voltage levels:
OUTPUT: LOGIC 1: 2.4-3.6V LOGIC 0: 0-0.4V INPUT: LOGIC 1: 2-3.6V (can be up to 5V for 5V tolerant inputs) LOGIC 0: 0-0.8V
Low voltage device families:
74ALB Advanced - Low Voltage - BiCMOS 74LV Low - Voltage 74LVU Low - Voltage (Unbuffered output) 74LVC Low voltage CMOS 74LVCR Low voltage CMOS with damping Resistor 74LVCU Low voltage CMOS with unbuffered output 74LVCH Low - Voltage - CMOS - bus Hold 74ALVC Advanced - Low - Voltage - CMOS 74LVT Low voltage TTL 74LVTR Low voltage TTL with damping Resistor 74LVTU Low voltage TTL with unbuffered output 74LVTZ Low - Voltage - TTL - High Impedance power-up 74ALVC Advanced - Low - Voltage - CMOS (bus Hold) 74ALVCR Advanced - Low - Voltage - CMOS (bus Hold) with damping Resistor 74ALVCH Advanced - Low - Voltage - CMOS - bus Hold 74LCX Low voltage CMOS (operates with 3V and 5V supplies) 74VCX Low voltage CMOS (operates with 1.8V and 3.6V supplies)
Very low voltage
The lowerung of operating voltages from 5V to 3V does not stop there. There is a trend of even lover operating voltages. Nowadays there are for example 2.5 V and 1.8 V logic families in use.
74VCX Low voltage CMOS (operates with 1.8V and 3.6V supplies)
- Useful Tips Ease Interfacing Of Logic Devices In Mixed 3-V And 5-V Systems Rate this link
- Clock Generation Interfacing for Mixed 3V and 5V Systems - In many system designs it may be advantageous or mandatory to use both five to three volt supply components. Most of the Frequency and Timing Generators (FTGs) that ICS produces will operate from both 5.0 (4.5 - 5.5V) and 3.3 (2.7 - 3.7V) volt power supplies. This application note suggests some recommended solutions, their implementation and important points to be considered when interfacing signals that must connect between clock generators, and logic circuits operating at different supply voltages. Rate this link
Mixed voltage systems
Operating voltages for digital systems have dropped from 5 V to 3 V or lower, because of the demand for higher-speed logic families that use ICs with smaller geometries. In many designs, however, 3-V systems coexist with legacy 5-V systems, and both supply voltages are mixed on the same circuit board. With the introduction of even lower voltage standards, such as 2.5 V and 1.8 V, it can be expected that mixed voltage interfacing issues will be around for many years.
There are pitfalls to watch out for when interfacing mixed-voltage systems. These pitfalls can be avoided by paying close attention to a few key issues. These include the maximum voltages applied to the input and output pins, the current flowing between the power supplies, and the input-switching threshold levels that must be met.
Popular digital interfaces
Besides what is offered by the different logic IC families there are some popular digital interface standards in use that use different signal levels or way opf signaling than any logic family. For example many interfaces that go beyond the internals of electronics device need something more robust interface than what logic families can themselves can offer. Usually in external interfaces the digital logic signal are converted with some interfacing IC to something suitable in the transmitting end and back to normal logic signal on the receiving end. For example RS-232 serial communications interfacing works in this way (the signals on the line are normally +12V or -12V).
Here are some information on some loginc interfaces used in inter-system interfacing applications.
The most common serial interface used today by computer manufacturers is the RS-232. This serial interface found on practically every PC and external modem (and many other devices). RS-232 is simple, universal, well understood and supported everywhere.
The RS-232 standard was originally issued in 1969 by EIA (Electronics Industries Association) for single purpose: to interconnect terminals (Data Terminal Equipment, DTE) to data communication devices (Data Communication Equipment, DCE) like modems. When RS-232 is used to interface terminals to modems, it is simply connecting respective pins in the two devices (modem and terminal). However. RS-232 is often used to interconnect terminals to computers or computers to peripheral equipment. The standard never specified such options, so this kind of interfacing usually requires special consideration (sometimes special custon cables like "null modem" or similar).
RS232 defines the electrical and physical standard (standard specifies 25 pin connector).
The essential feature of RS-232 is that the signals are carried as single voltages referred to a common earth on pin 7 on 25 pin connector (pin 5 on 9-pin connector). The output signal level usually swings between +12v and -12v. In RS-232 anythugh higher than +3V is considered to be logic 0 and anything lower than -3V is considered to be logic 1. The "dead area" between +3v and -3v is designed to absorb line noise. In the various RS-232-like definitions this dead area may vary. For instance, the definition for V.10 has a dead area from +0.3v to -0.3v. Many receivers designed for RS-232 are sensitive to differentials of 1 volt or less.
Since different logic families work at different voltage levels it is somewhat complicated to interface components from different families together.
When designing high-speed systems, people often encounter the problem of how to connect different ICs with different interfaces. To deal with this, it is important to understand the input and output circuit configurations of each interface for proper biasing and termination.
ECL, 5 and 3.3V PECL, LVDS, and some GaAs families work with roughly 1V signal swings on 100. differential traces. Although the dc-bias levels of these circuits differ, as long as you select a dc balanced code, you may use dc-blocking capacitors to interconnect any of these logic families.
One of those discarded ideas was to move beyond binary logic to circuits based on multi-valued logic in which the information density and processing efficiency of a circuit could theoretically be increased substantially without any further expensive "improvements" to the underlying fabrication technology.
There are techniques to make ICs that can reliably generate multiple signal levels that are easily discriminated. Semiconductor companies have started investigating on ternary and quaternary logic circuits. Not only do we have SiGe transistor structures that are inherently friendly to multi-valued logic, the industry has become quite good at generating and discriminating multiple voltage and current thresholds. Intel, Fairchild, National Semiconductor, Signetics (now Philips), and Motorola all have products on the market that had ternary or quaternary logic hidden inside. It seems that economics of semiconductor manufacturing now is forcing us to move beyond zero and one.
The performance of two level binary logic is limited due to interconnects which occupy a large area on a VLSI chip. In a VLSI circuit, approximately 70 percent of the area is devoted to interconnection, 20 percent to insulation, and 10 percent to device. One can achieve a more cost-effective way of utilizing interconnections by using a larger set of signals over the same area in multiplevalued logic (MVL) devices.
There are still challenges if multilevel logic comes to use besides the technology itself. Binary logic way of thinking that has become second nature to the electronics and computer engineers, so the designers can't quicly adapt to somthign different. Despite the fact that all of the theoretical work on multi-valued logic that is available, will engineers be willing to move away from the safe world of binary logic? The way that Intel and other companies have got beyond that problem is to keep the engineer away from the ternary and quaternary logic, incorporating interface circuits that converted signals into and out of the multi-threshold core.
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