Parallax Propeller 1 Goes Open Source

Parallax Propeller is multi-core microcontroller development platform. The Parallax P8X32A Propeller chip, introduced in 2006, is a multi-core architecture parallel microcontroller with eight 32-bit RISC CPU cores. It can be programmed for example with Propeller Assembly language, Spin interpreter and C programming languages.

propeller

Interesting news on this platform is that Parallax Propeller 1 Goes Open Source. On August 6, 2014, Parallax Inc. released the Propeller P8X32A Verilog and top-level HDL files under the GNU General Public License 3.0. I think it is a trust and an ecosystem thing: while is has a loyal following with hobbyists, it really hasn’t ever hit the big time. Propeller isn’t like traditional microcontroller, so it is a bit of a business risk to have vendor lock-in. Now you now no longer have to worry about second sourcing this part even if it went EOL.

If you are open hardware experimenter, you can now build a device that is open hardware, open code all the way down to the CPU level! Either use a product CPU, and have access to it’s source code to understand what and how it does things, or load that CPU onto a suitable FPGA and modify it or combine it with your design. By releasing the chip design, they would encourage people to try it out (as it is sold no or in a FPGA). Maybe this is way to try to survive on the market that is being taken over by different variations of ARM.

 

4 Comments

  1. Tomi Engdahl says:

    FPGA with Open Source Propeller 1 Running Spin
    http://hackaday.com/2014/08/24/fpga-with-open-source-propeller-1-running-spin/

    Open Sourcing something doesn’t actually acquire meaning until someone actually uses what has been unleashed in the wild. We’re happy to see a working example of Propeller 1 on an FPGA dev board.

    You’ll remember that Parallax released the Propeller 1 as Verilog code a few weeks back. This project first loads the code onto the FPGA, then proves it works by running SIDcog, the Commodore 64 sound emulation program written in Spin for p8x32a processors.

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  2. Tomi Engdahl says:

    Improving the Parallax Propeller in an FPGA
    http://hackaday.com/2014/10/30/improving-the-parallax-propeller-in-an-fpga/

    The Parallax Propeller is an interesting chip that doesn’t get a lot of love, but since the entire chip was released as open source, that might be about to change: people are putting this chip inside FPGA and modifying the binaries to give the chip functions that never existed in the original.

    Last August, Parallax released the source for the P8X32A, giving anyone with an FPGA board the ability to try out the Prop for their own designs.

    Parallax Propeller P8X32A-V With Addons
    http://syso.name/s/parallax-propeller-p8x32a-v-with-64-i-o/

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  3. Tomi Engdahl says:

    Startup to Open Source Parallel CPU
    Rex targets 10x leap in performance/watt
    http://www.eetimes.com/document.asp?doc_id=1324759&

    A startup founded by two teenagers is designing a parallel processor that it hopes delivers a 10x leap in performance per watt for high-end systems. Rex Computing will make open source its instruction set architecture in hopes of rallying supporters around it.

    The startup’s ambitions are high, as explained by chief executive Thomas Sohmers, who recently became old enough to sign the company’s contracts. He aims to create an alternative to today’s processors and accelerators, which are too expensive (mainly in power consumption) to scale to the exaflop performance researchers hope to deliver in the next decade.

    Sohmers was recently elected co-chairman of the high-performance working group under the Open Compute Project (OCP) started by Facebook. He hopes Rex can finish the design of its neo core as early as January and make it open source through the group.

    The 3W Neo chip (above) packs into 80 mm2 256 cores, each consisting of a 64-bit ALU, IEEE floating point unit, and 128 Kbits of SRAM scratch pad memory. Each core has a 16 Gbyte/s link to its neighbors with about 384 Gbytes/s of aggregate bandwidth between chips.

    Sohmers was inspired by Adapteva’s Epiphany chip, on which he based his first prototypes.

    http://www.rexcomputing.com/

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