SiFive Unveils the First RISC-V-Based Arduino

https://blog.hackster.io/sifive-unveils-the-first-risc-v-based-arduino-a4d07fe7f21f

 “Arduino Cinque” is based on SiFive’s Freedom E310 — the industry’s first commercially available RISC-V core — running at 320MHz. Aside from the SoC, an onboard ESP32 chip provides support for 2.4GHz Wi-Fi and Bluetooth.

3 Comments

  1. Tomi Engdahl says:

    Arduino Cinque – The RISC-V, ESP32, WiFi, Bluetooth Arduino
    http://hackaday.com/2017/05/20/arduino-cinque-the-risc-v-esp32-wifi-bluetooth-arduino/

    This weekend at the Bay Area Maker Faire, Arduino in conjunction with SiFive, a fabless provider of the Open Source RISC-V micros, introduced the Arduino Cinque. This is a board running one of the fastest microcontrollers available, and as an added bonus, this board includes Espressif’s ESP32, another wonderchip that features WiFi and Bluetooth alongside a very, very powerful SoC.

    Details on the Arduino Cinque are slim at the moment, but from what we’ve seen so far, the Cinque is an impressively powerful board featuring the RISC-V FE310 SoC from SiFive, an ESP32, and an STM32F103. The STM32 appears to be dedicated to providing the board with USB to UART translation, something the first RISC-V compatible Arduino solved with an FTDI chip.

    Manufacturing Your Own Chips: Is Open Source (like RISC-V) Making it Easier?
    http://makerfaire.com/maker/entry/60546/

    Reply
  2. Tomi Engdahl says:

    RISC-V Pros And Cons
    https://semiengineering.com/risc-v-pros-cons/

    Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?

    Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation.

    “The money shouldn’t be going into the processors, necessarily,” said Ted Speers, senior technical director, product architecture and planning for Microsemi‘s SoC business unit, and board member of RISC-V Foundation. “The processor cost should come down, and then you innovate on top of that with accelerators, new architectures, and so forth.”

    Technically, the ability to manage complexities has expanded to the point where a 32-bit RISC microprocessor is not considered a complex object anymore, noted Drew Wingard, CTO of Sonics.

    “The barrier to entry as a microprocessor instruction set architecture is all about the software and the ecosystem,” he said. “There’s no magic in the underlying technology for microprocessors, in general. RISC-V essentially takes that to the next logical level to say,

    The business end of this market will likely the same model as Linux, where commercial vendors add in their own IP and support. Commercial suppliers of RISC-V cores include Nvidia, Andes Technology, Cortus, and Codasip.

    The main ISAs used today are x86, ARM, ARC, MIPS and PowerPC, along with other ISAs used under the hood in GPUs and DSPs. But RISC-V is starting to make some inroads. Nvidia announced that its SoCs will contain a RISC-V control processor. Andes Technology, a softcore supplier, likewise adopted RISC-V in its 64-bit architecture.

    RISC-V from an architecture standpoint, is both simple and elegant

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  3. Tomi Engdahl says:

    SiFive’s Chief Executive on Opening a Chip Design Factory
    http://www.electronicdesign.com/embedded-revolution/sifive-s-chief-executive-opening-chip-design-factory

    Before he agreed to anything, Naveed Sherwani needed to make 40 phone calls. He had questions about the new RISC-V computer architecture and the company founded by its inventors, SiFive. He had been asked to run it.

    Sherwani, a founder of Open Silicon, called venture capitalists and semiconductor executives, who agreed unanimously that the free and open architecture had serious potential. “I was expecting half the people to tell me, ‘I don’t know, it’s kind of a new experiment.’ That’s typical when you are starting a new venture,” he said in an interview.

    SiFive is using the RISC-V architecture in an attempt to make custom chips more affordable and to eliminate common annoyances with licensing other architectures like ARM and MIPS.

    The company has already “made the front-end part of the design extremely efficient,” Sherwani said. “We are now working on the back-end process – the verification process – to create what we would call a chip design factory, which would allow people to do custom silicon extremely fast.”

    SiFive plans to make money by providing customization and support around RISC-V

    SiFive also wants to act like a clearinghouse for intellectual property. The company charges a one-time payment less than a million dollars to license its unique cores for data center and Internet of Things applications. Last week, it introduced a program called DesignShare to provide blueprints from companies – like Rambus – at lower cost or for free.

    Going forward, SiFive will need to find a way to translate the enthusiasm for RISC-V into paying customers. The RISC-V Foundation, which maintains the instruction set, includes members like Google, Microsoft, Oracle, and IBM. Microsemi has signed on SiFive’s first major customer.

    When asked why he thought SiFive would succeed, Sherwani said that the company could follow the open-source software model, which was not as widespread when other open-source architectures like OpenSPARC came out.

    Reply

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