HiFive1 Is an Open-Source, Arduino-Compatible RISC-V Dev Kit



  1. Tomi Engdahl says:

    HiFive1: RISC-V In An Arduino Form Factor

    The RISC-V ISA has seen an uptick in popularity as of late — almost as if there’s a conference going on right now — thanks to the fact that this instruction set is big-O Open. This openness allows anyone to build their own software and hardware. Of course, getting your hands on a RISC-V chip has until now, been a bit difficult. You could always go over to opencores, grab some VHDL, and run a RISC-V chip on an FPGA. Last week, OnChip released the RISC-V Open-V in real, tangible silicon.

    Choice is always a good thing, and now SiFive, a fabless semiconductor company, has released the HiFive1 as a crowdfunding campaign on CrowdSupply. It’s a RISC-V microcontroller, completely open source, and packaged in the ever so convenient Arduino form factor.

    The heart of the HiFive1 is SiFive’s FE310 SoC, a 32-bit RISC-V core running at 320+ MHz. As far as peripherals go, the HiFive1 features 19 digital IO pins, one SPI controller, 9 PWM pins, an external 128Megabit Flash, and five volt IO. Performance-wise, the HiFive1 is significantly faster than the Intel Curie-powered Arduino 101, or the ARM Cortex M0+ powered Arduino Zero. According to the crowdfunding campaign, support for the Arduino IDE is included. A single HiFive1 is available for $59 USD.

  2. Tomi Engdahl says:

    RISC-V Expands its Audience
    Workshop attracts chip architects, execs

    The RISC-V movement is grabbing the attention of a growing set of chip architects and semiconductor executives. Several came to the group’s fifth workshop here to gauge whether the seeds planted by a handful of academics could grow into a disruptive, commercial reality.

    The group aims to spread support for its free instruction set architecture across a broad range of products. Talks at the event made clear it will take several years for the ambitious efforts to bear fruit.

    Many attendees said they felt exhilarated by the prospects of free, flexible cores unencumbered by patents with an ecosystem of innovations around them. Some feared the efforts could undermine existing markets in an industry already tightening its belt in a cold winter of consolidation.

    “RISC-V is the Linux of processor architectures,”

    “This event has the same feel to me as the early Linux gatherings in the 1990’s,” Minnich told EE Times. “You could tell something was happening, but you didn’t know where it was going to go, just that things were going to change,” he said.

    A graphics processor architect for AMD said RISC-V creates a welcome opportunity to try new ideas that would not fly in big companies. He noted a proposal at the event for RISC-V vector instructions contained useful concepts that were quite different from existing Intel and AMD approaches.

    Steve Wallach, a veteran system designer now at Micron, presented ways to use 128-bit addressing to create new levels of security.

    “But like the early days of Linux, [RISC-V] is not really real yet,” said Minnich. “You don’t know what DRAM controller or DRAM to use, and the current chips are tiny 32-bit embedded micros, so we’re still a few years off,” he said.

    The big news from the event was the release of a run of about 250 Arduino boards sporting a 32-bit RISC-V microcontroller from SiFive, a startup that released RTL code for its chip. A larger run is expected in February which may drive board costs down to $39.

    While a welcome milestone, several developers at the event said what they really longed for was a 64-bit processor that can run Linux.

    “We want real hardware,” said one Google developer presenting work on porting its Go language to RISC-V using FPGA simulators. “Don’t we all,” responded an audience member, sparking a round of laughs.

    SiFive is working on just such a board, likely to be unveiled next year. It demoed an FPGA version of its 64-bit, 28nm Freedom Unleashed design booting Linux and running “Doom.”

    A group at Cambridge University is not far behind. It aims to release in February an FPGA development board running its 64-bit Low RISC design and launch a crowd-funding campaign to pay for making an ASIC version.

    It’s unclear how the initial boards will compare with existing ARM and x86 products. Experts say an instruction set is relatively neutral, and implementation choices determine performance. One academic effort showed Coremark/MHz figures that surpassed an ARM Cortex A-15 and approached an Intel Ivy Bridge Xeon.

    Proponents also must port a wealth of existing software to RISC-V, a daunting task that has contributed to the slow advance of ARM’s effort to enable server-class SoCs. Much work on RISC-V software has already been done despite the lack of commercial hardware.

    A significant last mile hurdle stands in the way of anyone wanting a completely open source processor. There are no open source analog or mixed-signal blocks, and foundries have patents associated with their standard cell and I/O libraries.

    Given the costs of making chips, some wonder whether the comparison of RISC-V to Linux is a realistic one.

    Despite the issues, the movement is gaining traction. The RISC-V Foundation maintaining the spec has more than 50 paying members including companies such as AMD, Google, Hewlett Packard Enterprise, Huawei, IBM, Microsoft, Micron, Nvidia, NXP and Qualcomm.

    The latest event attracted 354 registrations from 107 companies.

    “Open source [hardware] is a new thing,”

    “If you lay back, this thing will fail,”

  3. Tomi Engdahl says:

    Programming the Open-V Open Source CPU on the Web

    You can now program the Open-V on the web, and see the results in real time. The code is compiled in the web IDE and then flashed to a microcontroller which is connected to a live YouTube live stream. It’s pretty neat to flash firmware on a microcontroller thousands of miles away and see the development board blink in response.


  4. Tomi Engdahl says:

    Will this number-generation innovation hack off the hackers?

    Universidad Industrial de Santander in Columbia. The team there has developed a security building block for the Open-V microprocessor with a fully open True Random Number Generator (TRNG) peripheral.

    A TRNG is a RNG that produces bits based on a random physical process.
    security building block can generate up to 400,000 random bits/sec and needs a mere 0.01mm2 of die space.

  5. Tomi Engdahl says:

    SiFive Coreplex IP designs have become the leader for RISC-V cores

    The RISC-V open-source architecture, created by researchers at the University of California, Berkeley, in 2010, is open to all who want to use it. The RISC-V design can be modified for PCs, servers, smartphones, wearables, and other devices.

    RISC-V shares the ethos of open-source software, with the community working together to share, advance, and modify the architecture.

    Since the project’s inception, the interest in RISC-V has ballooned, with some of the big IT companies (like Google, Nvidia, AMD, Microsoft…) showing interest in the architecture.

    A startup called SiFive is the first to make a business out of the RISC-V architecture. The company is also the first to convert the RISC-V instruction set architecture into actual silicon.

  6. Tomi Engdahl says:

    Agam Shah / PCWorld:
    SiFive, creators of open RISC-V architecture, announce $8.5M Series B led by Spark Capital as company unveils two new chip designs

    Open-source chip mimics Linux’s path to take on closed x86 and ARM CPUs
    The RISC-V chip design can be licensed from SiFive


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