https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
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Tomi Engdahl says:
EEVblog #1155 – Mailbag
https://www.youtube.com/watch?v=XrhCGrZyIVM
Sipeed MAIX : The World First RISC-V 64 AI Module for edge computing:
https://www.indiegogo.com/projects/sipeed-maix-the-world-first-risc-v-64-ai-module#/
Tomi Engdahl says:
OpenISA Launches New, Free RISC-V VEGAboard
https://abopen.com/news/openisa-launches-new-free-risc-v-vegaboard/
OpenISA has officially launched the VEGAboard microcontroller development board, based on the PULP Platform’s RI5CY and Zero-RI5CY RISC-V core, and it’s giving them away to encourage adoption of the free instruction set architecture (ISA).
Tomi Engdahl says:
PULP Platform
Open hardware, the way it should be!
https://pulp-platform.org
Tomi Engdahl says:
Design Your Own CPU!!!
https://m.youtube.com/watch?v=jNnCok1H3-g
We get a look at some working Open Source silicon and the things people are doing with the technology.
Tomi Engdahl says:
Libre RISC-V M-Class
A 100% libre RISC-V + 3D GPU chip for mobile devices
https://www.crowdsupply.com/libre-risc-v/m-class
Tomi Engdahl says:
Open-Source RISC-V Hardware And Security
https://semiengineering.com/security-and-open-source-hardware/
Experts at the Table, Part 1: The advantages and limitations of a new instruction set architecture.
SE: Is open-source hardware more secure, or does it just open up vulnerabilities to a much wider audience of cyber criminals?
Newell: We deal a lot with governments and defense customers. They have a tendency to believe everything should be secret. I take more of a middle ground view, which recognizes that complex systems are going to have bugs. In that case, secrecy can improve your security. But security systems can be protected by open source and improved. Any real security has to include simpler elements that protect the more complex systems.
Handschuh: With open source, you have the opportunity to review it and come up with comments, feed it back to the community, and as a group you can advance maybe not faster but better. You have more hands. Everybody is available to give you constructive comments, and then you can work together to make it better. That means you start from something that is open and published, and then you evolve it together by adding things and creating white papers.
Kiniry: Our government trends toward not having artifacts being public, but they definitely want to see everything. Openness helps with them as a client.
SE: If you are updating open source that is public, that may be great. But when hackers find vulnerabilities, they don’t necessarily publish those. So now a lot more is exposed for everyone to see. Is that worse than proprietary instruction set architectures?
Handschuh: By publishing the interfaces you get more people to look at it. Hiding things behind the scenes is worse because then you don’t know what’s going on.
Newell: There are different ways to analyze this. Formal analysis is certainly a good way. A lot of eyes on it is another good way. We are going down a formal route. We have a formal committee that is providing a description of the ISA interface. And then you need to look at the microkernel. But as soon as you get to a rich OS like Linux, you’re never going to be able to solve the bugs. If you look at set-top boxes, a lot of those hacks happened because the software was reverse-engineered. There is a place for secrecy, at least as a road bump to slow down these guys.
Kiniry: The struggle I see is at the intersection of policy and technology. With our current leadership, there is a tendency to hold vulnerabilities close to the vest. If the government finds problems, especially with hardware, we’re not guaranteed we will learn about them—even in the case of open systems. That’s problematic.
Tomi Engdahl says:
UltraSoC’s Gadge Panesar looks at using RISC-V alongside Arm cores and argues for heterogeneous architectural and modeling exploration systems and the importance of open APIs.
Systemic complexity: time for RISC-V to rise to the challenge
https://www.ultrasoc.com/systemic-complexity-time-for-risc-v-to-rise-to-the-challenge/
But as we look forward to a bright future for RISC-V, it’s important to focus on what really matters. For chip architects and designers today, “the ISA” is a small consideration. The concern isn’t even choosing “the core”. Designers today are faced by a “whole system” problem: a problem of systemic complexity.
Tomi Engdahl says:
RISC-V Summit was a Haunting Experience (With Apologies to Charles Dickens)
https://www.eeweb.com/profile/loucovey/articles/risc-v-summit-was-depressing-with-apologies-to-charles-dickens
Tomi Engdahl says:
More Than A Core
https://semiengineering.com/more-than-a-core/
A system-level look at integration, security, and new architectures such as RISC-V.
Tomi Engdahl says:
RISC-V Summit was a Haunting Experience (with Apologies to Charles Dickens)
https://www.eeweb.com/profile/loucovey/articles/risc-v-summit-was-depressing-with-apologies-to-charles-dickens
There was a lot of talk about ‘opportunities and challenges’ at the RISC-V Summit, but security was low on the list for opportunities and glossed over in regard to challenges
Tomi Engdahl says:
“A RISC-V-based Raspberry Pi isn’t a totally crazy idea. Indeed in the long run, it might even be an obvious one?”
Raspberry Pi Becomes a Member of the RISC-V Foundation
https://blog.hackster.io/raspberry-pi-becomes-a-member-of-the-risc-v-foundation-11f06aecc241
Tomi Engdahl says:
Building Security Into RISC-V Systems
https://semiengineering.com/building-security-into-risc-v-systems/
Experts at the Table, part 2: Emphasis shifting to firmware, system-level architectures, and collaboration between industry, academia and government.
Tomi Engdahl says:
OpenISA Launches Free RISC-V VEGAboard
https://hackaday.com/2019/02/04/openisa-launches-free-risc-v-vegaboard/
RISC architecture is gonna change everything, and I still can’t tell if we like that movie ironically or not. Nevertheless, RISC-V chips are coming onto the market, chipmakers seem really interested in not paying licensing fees, and new hard drives are shipping with RISC-V cores. The latest development in Open instruction sets chips comes from OpenISA. They’ve developed the VEGAboard, a dev board with two RISC-V chips and Arduino-style pin headers.
The VEGAboard comes loaded with an NXP chip which combines an ARM Cortex-M0 and Cortex-M4. So far, so good, but there are already dozens of boards that combine two ARM microcontrollers on a single development platform. The real trick is the RI5CY and Zero-RI5CY chips on the VEGAboard, a 4-stage RISC-V RV32IMCCXpulp CPU.
https://open-isa.org/
Tomi Engdahl says:
PULP – An Open Parallel Ultra-Low-Power Processing-Platform
http://iis-projects.ee.ethz.ch/index.php/PULP
Tomi Engdahl says:
You Can Now Build a RISC-V PC That Runs Fedora Linux
https://blog.hackster.io/you-can-now-build-a-risc-v-pc-that-runs-fedora-linux-with-an-fpga-97cd5789b28
Tomi Engdahl says:
New Part Day: The RISC-V Chip With Built-In Neural Networks
https://hackaday.com/2018/10/08/new-part-day-the-risc-v-chip-with-built-in-neural-networks/
Tomi Engdahl says:
https://semiengineering.com/week-in-review-design-low-power-29/
AdaCore says it is working with NVIDIA to implement Ada and Spark programming languages in some of NVIDIA’s security-critical firmware used in safety- and security-critical applications, such as automated and autonomous driving. NVIDIA is migrating some of its SoCs to the open-source RISC-V instruction set architecture and rewriting some of its security firmware from C to Ada and Spark.
Tomi Engdahl says:
RISC-V Will Stop Hackers Dead From Getting Into Your Computer
https://hackaday.com/2018/12/13/risc-v-will-stop-hackers-dead-from-getting-into-your-computer/
RISC-V researchers are busy creating an Open Source hardware enclave. This is an Open Source project to build secure hardware enclaves to store cryptographic keys and other secret information, and they’re doing it in a way that can be accessed and studied. Trust but verify, yes, and that’s why this is the most innovative hardware development in the last decade.
https://keystone-enclave.org/
Tomi Engdahl says:
RISC-V on the Verge of Broad Adoption
https://www.eetimes.com/document.asp?doc_id=1334311#
There are several reasons the RISC-V ISA has been garnering a lot of interest.
The ISA is defined for 32-, 64-, and 128-bit implementations with code for the smaller bit widths executable on larger-base implementations.
Basic ports of Linux, GNU-based development tools, and several core designs are already available from the open source community. In addition, companies such SiFive, NXP, Kendryte, and GreenWaves Technologies have created commercially-available RISC-V chips. Other companies, like Nvidia and Western Digital, have begun to embrace RISC-V in developing processors for their internal use, replacing proprietary designs. Commercial software development is also underway, with Adacore working to bring the Ada and Sparc programming languages to RISC-V for safety and security-critical applications.
Tomi Engdahl says:
Kendryte’s KD233 Is a Dual-Core RISC-V SoC Designed for AI Applications
https://blog.hackster.io/kendrytes-kd233-is-a-dual-core-risc-v-soc-designed-for-ai-applications-2ed75199b4c4
There are several RISC-V development boards on the market (or are about to be released) that use the open instruction set architecture (ISA) — including SiFive’s HiFive and HiFive Unleashed, and GreenWaves’ GAP8 development board. We can add another RISC-V-based development board to that list, with the introduction of Kendryte’s KD233 SoC, which was designed for machine vision and learning.
Tomi Engdahl says:
Creating a custom processor with RISC-V
https://www.edn.com/design/systems-design/4461561/Creating-a-custom-processor-with-RISC-V?utm_source=Aspencore&utm_medium=EDN&utm_campaign=social
With its blend of open-source freedoms with the benefits of standardization, the RISC-V (risk-five) Foundation is attracting widespread industry interest
Tomi Engdahl says:
RISC-V on the Verge of Broad Adoption
https://www.eetimes.com/document.asp?doc_id=1334311
Tomi Engdahl says:
OneSpin unveiled a set of formal apps for development and assessment of RISC-V cores. The RISC-V Integrity Verification Solution formalizes the RISC-V ISA in a set of SystemVerilog Assertions to verify compliance for the ISA is met. It provides a formal bug absence core assessment environment for unbounded proofs and systematic discovery of all hidden instructions or unintended side effects and also verifies that cores do not contain hardware Trojans or other unintended functionality.
Source: https://semiengineering.com/week-in-review-design-low-power-31/
More:
OneSpin Launches First Formal RISC-V Integrity Verification Solution
https://www.onespin.com/press-events/press-releases/details/news/detail/News/onespin-launches-first-formal-risc-v-integrity-verification-solution/
Tomi Engdahl says:
UltraSoC announced its embedded analytics architecture fully supports Western Digital’s RISC-V SweRV Core and associated OmniXtend cache-coherent interconnect.
UltraSoC announces support for Western Digital RISC-V SweRV Core and OmniXtend cache-coherent interconnect
https://www.ultrasoc.com/ultrasoc-announces-support-for-western-digital-risc-v-swerv-core-and-omnixtend-cache-coherent-interconnect/
Tomi Engdahl says:
How Open Source Hardware Empowers Procurement
https://epsnews.com/2019/02/19/open-source-empowers-procurement/
Tomi Engdahl says:
How to Connect Questa VIP to the Processor Verification Flow
https://semiengineering.com/how-to-connect-questa-vip-to-the-processor-verification-flow/
Step-by-step RISC-V tutorial guides you through concepts of combining automatically generated UVM with QVIP.
How to Connect Questa® VIP to the Processor Verification Flow
https://www.codasip.com/2018/01/04/how-to-connect-questa-vip-to-the-processor-verification-flow/
Learn how to incorporate Questa® VIP into your existing RISC-V verification flow. The tutorial, prepared by Codasip’s verification experts, explains the concepts of combining automatically generated UVM with QVIP and guides you through the process.
Tomi Engdahl says:
Amazon adds RISC-V support to the FreeRTOS kernel, including preconfigured examples for the Open-isa.org VEGAboard, QEMU emulator for SiFive’s HiFive board, and Antmicro’s Renode emulator for the Microchip Makes M2GL025 Creative Board.
New – RISC-V Support in the FreeRTOS Kernel
https://aws.amazon.com/blogs/aws/new-risc-v-support-for-freertos-kernel/
Tomi Engdahl says:
https://www.edn.com/design/systems-design/4461561/Creating-a-custom-processor-with-RISC-V?utm_source=Aspencore&utm_medium=EDN&utm_campaign=social
Tomi Engdahl says:
The Challenge Of RISC-V Compliance
https://semiengineering.com/toward-risc-v-compliance/
Showing that a processor core adheres to a specification becomes more difficult when the specification is extensible.
Tomi Engdahl says:
The Rapid Rise Of RISC-V
https://semiengineering.com/the-rapid-rise-of-risc-v/
The open source ISA’s ecosystem takes big steps forward with the latest foundation member announcements.
Tomi Engdahl says:
Formal Verification Of RISC-V Cores
https://semiengineering.com/formal-verification-of-risc-v-cores/
As RISC-V offerings expand, it’s vital to make sure they conform to the ISA specification.
Tomi Engdahl says:
Debug Platform Supports Western Digital RISC-V Core
https://www.eeweb.com/profile/eeweb/news/debug-platform-supports-western-digital-risc-v-core
UltraSoC’s embedded analytics architecture allows developers working with Western Digital’s RISC-V SweRV core and associated OmniXtend cache-coherent interconnect to debug their designs using either a standards-based or proprietary approach. Both companies have worked together to create a debug and on-chip analytics ecosystem that not only supports internal development teams, but also third parties looking to adopt the SweRV core for their own applications.
UltraSoc’s RISC-V processor trace tool allows the behavior of a program to be viewed in detail, key for system developers.
Tomi Engdahl says:
Introducing RISC-V and RISC-V Tools
https://www.eeweb.com/profile/max-maxfield/articles/introducing-risc-v-and-risc-v-tools
Tomi Engdahl says:
A New RISC-V-Based AI HAT for the Raspberry Pi From Seeed Studio
https://blog.hackster.io/a-new-risc-v-based-ai-hat-for-the-raspberry-pi-from-seeed-studio-6ca6ac5af7ce
Towards the tail end of last year, Sipeed released their 64-bit RISC-V MAix module, crowdfunding a range of boards on Indiegogo. Now Seeed Studio is going to make a Grove HAT for Raspberry Pi based on the MAix.
Tomi Engdahl says:
Intel, RISC-V Rally Rival Groups
CXL, CHIPS Alliance extend competing processor ecosystems
https://www.eetimes.com/document.asp?doc_id=1334416
Intel and RISC-V backers announced rival alliances to nurture competing ecosystems around tomorrow’s processors.
Intel initiated Compute Express Link (CXL), an open chip-to-chip interconnect that it expects to use on its processors starting in 2021 to link to accelerators and memories. Other members include Alibaba, Cisco, Dell EMC, Facebook, Google, HPE, Huawei, and Microsoft.
Separately, a handful of RISC-V proponents launched the CHIPS Alliance, a project of the Linux Foundation to develop a broad set of open-source IP blocks and tools for the instruction set architecture. Initial members include Esperanto, Google, SiFive, and Western Digital. CHIPS stands for Common Hardware for Interfaces, Processors, and Systems.
The CHIPS Alliance is, by far, the most ambitious of the two efforts and is just one of several open-hardware initiatives in the works at the Linux Foundation.
Tomi Engdahl says:
Linux Foundation to Host CHIPS Alliance Project to Propel Industry Innovation Through Open Source Chip and SoC Design
https://www.linuxfoundation.org/press-release/2019/03/linux-foundation-to-host-chips-alliance-project-to-propel-industry-innovation-through-open-source-cpu-chip-and-soc-design/
Tomi Engdahl says:
Debug Platform Supports Western Digital RISC-V Core
https://www.eeweb.com/profile/eeweb/news/debug-platform-supports-western-digital-risc-v-core
UltraSoC’s embedded analytics architecture allows developers working with Western Digital’s RISC-V SweRV core and associated OmniXtend cache-coherent interconnect to debug their designs using either a standards-based or proprietary approach. Both companies have worked together to create a debug and on-chip analytics ecosystem that not only supports internal development teams, but also third parties looking to adopt the SweRV core for their own applications.
Tomi Engdahl says:
The Return of the RISC-V HiFive1
https://blog.hackster.io/the-return-of-the-risc-v-hifive1-359559b9aa6
Since the Bay Area startup SiFive announced the release of their Freedom Everywhere 310 (FE310) system-on-chip (SoC) — the industry’s first commercially-available SoC based on the open source architecture—back in 2016, the RISC-V architecture has undergone what can only be called a renaissance. After nearly a decade of neglect, the last two years has seen a big uptick in the adoption of the the RISC-V standard.
The release of the first Arduino-compatible development board, called the HiFive1, was seen as a real milestone
now SiFive is back with the HiFive1 Rev B, now raising on Crowd Supply.
the biggest obvious difference between the original HiFive1 board and the new Rev B is that unlike the older board, which operated at 1.8V, the new board supports 3.3V I/O on the GPIO pins only so that the pins can be driven directly from the F310.
Tomi Engdahl says:
Run a MicroPython NES Emulator on RISC-V Dev Boards
https://blog.hackster.io/run-a-micropython-nes-emulator-on-risc-v-dev-boards-f99c6feecae8
Tomi Engdahl says:
NES on RISC-V
https://hackaday.com/2019/03/14/nes-on-risc-v/
RISC architecture might change the world, but it runs an NES emulator right now. That’s thanks to MaixPy, the new MicroPython for the K210, the recently released RISC-V microcontroller that’s making waves in the community.
https://github.com/sipeed/MaixPy
Tomi Engdahl says:
New Part Day: The RISC-V Chip With Built-In Neural Networks
https://hackaday.com/2018/10/08/new-part-day-the-risc-v-chip-with-built-in-neural-networks/
After exploring a few random online shops one day, [David] (thanks for sending this in, by the way) ran across a very interesting chip. It’s a dual-core, RISC-V chip running at 400MHz. There’s 6 MB of SRAM on the CPU, and there’s 2MB for convolutional neural network acceleration. There is, apparently, WiFi on some versions. There are already SDKs available on GitHub, and a bare chip costs a dollar or two. Interested? Log in to Taobao, realize Taobao does pre-orders, and all this can be yours.
Tomi Engdahl says:
http://www.etn.fi/index.php/13-news/9224-linux-saatio-laajensi-avoimeen-rautaan
Tomi Engdahl says:
RISC-V opens up processor design
https://www.zdnet.com/article/risc-v-opens-up-processor-design/
Open source has comprehensively changed the world of software. RISC-V wants to do the same for processors.
Tomi Engdahl says:
Running FreeRTOS on the VEGA RISC-V Board
https://blog.hackster.io/running-freertos-on-the-vega-risc-v-board-8f38013d1af3
Tomi Engdahl says:
SiFive’s S2 RISC-V series claims to be the world’s smallest commercial 64-bit embedded core: http://bit.ly/2Z4KAhJ
https://www.sifive.com/press/sifive-launches-the-worlds-smallest-commercial-64-bit
Tomi Engdahl says:
With the support of Seeed Studio’s ArduinoCore-k210, you can now develop for RISC-V K210-based boards in the Arduino IDE: http://bit.ly/2v2TjTT
Grove Arduino Library for Kendryte K210
https://www.hackster.io/pillar-zuo/grove-arduino-library-for-kendryte-k210-d64918
Tomi Engdahl says:
SiFive launched its S2 Core IP series for power- and area-constrained high performance 64-bit embedded applications, providing an always-on low power CPU that can be combined with high-performance CPUs that switch on only when applications demand performance. The first IP in the line, S21, is based on the RV64IMAC ISA, includes 64-bit AXI Ports, machine and user mode with 4 region physical memory protection, and a 3-stage pipeline with simultaneous instruction and data access. The S2 Series will be available as a customizable Core IP Series as well as in the form of standard cores.
Source: https://semiengineering.com/week-in-review-design-low-power-38/
More:
SiFive Launches the World’s Smallest Commercial 64-bit Embedded Core
https://www.sifive.com/press/sifive-launches-the-worlds-smallest-commercial-64-bit
Tomi Engdahl says:
8 RISC-V Companies to Watch
https://www.designnews.com/electronics-test/8-risc-v-companies-watch?ADTRK=UBM&elq_mid=8276&elq_cid=876648
These eight companies are developing their own RISC-V technologies and are committing to helping third parties do the same to help push adoption of the open-source chip architecture.
RISC-V (pronounced “risk five”), the open-source architecture for chip design, has been making a lot of noise in the past few years. The open source nature of RISC-V promises to enable companies to create custom chip hardware specifically tailored to their products and devices.
Now, thanks much in part to the efforts of the RISC-V Foundation, an entire ecosystem of companies has sprung up, both of new startups and established chip and hardware companies, dedicated to leveraging the potential of open chip hardware for a variety of applications.
Tomi Engdahl says:
Now on GroupGets: RISC-V LoFive R1
https://blog.hackster.io/now-on-groupgets-risc-v-lofive-r1-8b820744c6a9
Tomi Engdahl says:
A New RISC-V-Based AI HAT for the Raspberry Pi From Seeed Studio
https://blog.hackster.io/a-new-risc-v-based-ai-hat-for-the-raspberry-pi-from-seeed-studio-6ca6ac5af7ce