https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
658 Comments
Tomi Engdahl says:
IAR toi työkalut RISC-V-kehitykseen
http://www.etn.fi/index.php/13-news/9502-iar-toi-tyokalut-risc-v-kehitykseen
Nyt ruotsalainen IAR System on laajentanut Embedded Workbench -työkalunsa tukmeaan myös RISC-V-piirien kehitystä.
Pakettiin kuuluvat C/C++-käännin sekä debuggeri eli virheenkorjaustyökalu. Testien mukaan IAR:n käännin tuottaa erittäin tiheää RISC-V-koodia, joka sopii pienempään muistiin mikro-ohjaimilla.
IAR Embedded Workbench for RISC-V -työkalujen ensimmäinen versio tukee 32-bittisiä RV32-ytimiä ja niiden laajennuksia
https://www.iar.com/iar-embedded-workbench/#!?architecture=RISC-V
Tomi Engdahl says:
New Part Day: A 64-Bit RISC-V CPU In Raspberry Pi Hat Form
https://hackaday.com/2019/05/24/new-part-day-a-64-bit-risc-v-cpu-in-raspberry-pi-hat-form/
Over the last few years the open-source RISC-V microprocessor has moved from existing only on FPGAs into real silicon, and right now you can buy a RISC-V microcontroller with all the bells and whistles you would ever want. There’s an interesting chip from China called the Sipeed M1 that features a dual-core RISC-V core running at 600MHz, a bunch of I/Os, and because it’s 2019, a neural network processor. We’ve seen this chip before, but now Seeed Studios is selling it as a Raspberry Pi Hat. Is it an add-on board for a Pi, or is it its own standalone thing? Who knows.
The Grove AI Hat for Edge Computing, as this board is called, is built around the Sipeed MAix M1 AI Module with a Kendryte K210 processor. This is a dual-core 64-bit RISC-V chip and it is obviously the star of the show here.
https://www.seeedstudio.com/Grove-AI-HAT-for-Edge-Computing-p-4026.html
Tomi Engdahl says:
Alibaba releases its first RISC-V CPU as open source solution for 5G and AI
https://www.techrepublic.com/article/alibaba-releases-their-first-risc-v-cpu-as-open-source-solution-for-5g-ai/
Alibaba’s investment in RISC-V could free them, and other Chinese companies, from licensing fees associated with the Arm ISA
Tomi Engdahl says:
https://en.wikipedia.org/wiki/RISC-V
Tomi Engdahl says:
https://www.techrepublic.com/article/alibaba-releases-their-first-risc-v-cpu-as-open-source-solution-for-5g-ai/
Tomi Engdahl says:
Alibaba’s chip division releases first core processor IP
https://www.bloomberg.com/news/articles/2019-07-11/mercedes-thieves-showed-just-how-vulnerable-car-sharing-can-be
Alibaba’s chip unit Pingtouge said its Xuantie 910 can serve advanced applications such as edge computing and autonomous driving and is based on RISC-V, an open source chip architecture developed by a consortium of tech companies and researchers.
Tomi Engdahl says:
https://blog.adafruit.com/2019/08/02/risc-architecture-is-gonna-change-everything-adafruit-joins-the-risc-v-foundation-risc_v-riscv-adafruit-adafruit/
Tomi Engdahl says:
“We’re going to start by introducing RISC-V-based chips to our Feather line of boards — there’s about 100 different mainboards, daughterboards, and accessories, so people can quickly get started integrating displays, sensors, and robotics with a RISC-V core.”
https://blog.hackster.io/adafruit-becomes-a-member-of-the-risc-v-foundation-7808c91db7b1
Tomi Engdahl says:
Adafruit Becomes a Member of the RISC-V Foundation
https://blog.hackster.io/adafruit-becomes-a-member-of-the-risc-v-foundation-7808c91db7b1
Tomi Engdahl says:
How to boot Linux on an open source RISC-V CPU, emulated in a FPGA, and the bitstream is generated with open source tools.
https://m.youtube.com/watch?feature=youtu.be&v=Ir_KBgbVr58
Tomi Engdahl says:
RISC-V Microprocessor Constructed with Carbon Nanotubes
https://blog.hackster.io/risc-v-microprocessor-constructed-with-carbon-nanotubes-75c1a6dc3921
http://www.epanorama.net/newepa/2019/08/29/a-carbon-nanotube-microprocessor-mature-enough-to-say-hello-ieee-spectrum-ieee-spectrum/
Tomi Engdahl says:
GigaDevice Unveils New RISC-V-Based GD32V Microcontroller
https://blog.hackster.io/gigadevice-unveils-new-risc-v-based-gd32v-microcontroller-c0a2b147568b
Several years ago China-based GigaDevice launched their GD32 microcontroller that took advantage of the ARB architecture and was compatible with STMicro’s STM32F103 microcontroller. The company is back with another GD32V series, only this time around they have dumped Arm in favor of RISC-V.
Tomi Engdahl says:
Sipeed’s Longan Nano is a $5 GD32V RISC-V dev board, with a 0.96″ LCD display and an acrylic case.
https://blog.hackster.io/seeed-releases-sipeeds-longan-nano-risc-v-development-board-18a041e8c440
https://blog.hackster.io/seeed-releases-sipeeds-longan-nano-risc-v-development-board-18a041e8c440
Tomi Engdahl says:
http://www.etn.fi/index.php/13-news/10003-ilmainen-tyokalu-nayttaa-miten-risc-v-piiri-operoi
https://www.segger.com/products/development-tools/systemview/
Tomi Engdahl says:
Creating a custom processor with RISC-V
https://www.edn.com/design/systems-design/4461561/Creating-a-custom-processor-with-RISC-V
Tomi Engdahl says:
Seeed Studio Announces GD32 RISC-V Development Board, Its Latest GigaDevice GD32V-Powered Design
https://www.hackster.io/news/seeed-studio-announces-gd32-risc-v-development-board-its-latest-gigadevice-gd32v-powered-design-0361c056bccd
Tomi Engdahl says:
Observer Simplifies Multi-Sensor Aggregation on FPGAs — By Giving Each Its Own RISC-V CPU
Designed to communicate with sensors that use different protocols, Observer offers easy aggregation without using too many resources.
https://www.hackster.io/news/observer-simplifies-multi-sensor-aggregation-on-fpgas-by-giving-each-its-own-risc-v-cpu-0c4bb9933b05
Tomi Engdahl says:
Running at up to 320MHz, SparkFun Electronics, Inc.’s RED-V Thing Plus and RedBoard feature a 32-bit RISC-V core in Adafruit Industries Feather- or Arduino Uno-like form factors.
SparkFun Picks SiFive’s FE310 to Power RISC-V-Based RED-V Thing Plus, RED-V RedBoard Dev Boards
https://www.hackster.io/news/sparkfun-picks-sifive-s-fe310-to-power-risc-v-based-red-v-thing-plus-red-v-redboard-dev-boards-c321292f9781
Running at up to 320MHz, the RED-V Thing Plus and RedBoard feature a 32-bit RISC-V core in Feather- or Arduino Uno-like form factors.
Tomi Engdahl says:
U.S.-based chip-tech group moving to Switzerland over trade curb fears
https://www.reuters.com/article/us-usa-china-semiconductors-insight/us-based-chip-tech-group-moving-to-switzerland-over-trade-curb-fears-idUSKBN1XZ16L
The nonprofit RISC-V Foundation (pronounced risk-five) wants to ensure that universities, governments and companies outside the United States can help develop its open-source technology, its Chief Executive Calista Redmond said in an interview with Reuters.
She said the foundation’s global collaboration has faced no restrictions to date but members are “concerned about possible geopolitical disruption.”
Tomi Engdahl says:
http://www.elektroniikkalehti.fi/index.php/13-news/10176-risc-v-muuttaa-sveitsiin-pakenee-trumpia
Tomi Engdahl says:
Low-power graphics specialist Think Silicon has announced it will be demonstrating its first 3D-capable graphics processor built on the free and open RISC-V instruction set architecture.
Think Silicon Unveils NEOX|V, Its First RISC-V-Based 3D-Capable GPU Family
https://www.hackster.io/news/think-silicon-unveils-neox-v-its-first-risc-v-based-3d-capable-gpu-family-8f03185fc1fa
Based on a 64-bit RISC-V implementation, Think Silicon’s GPU includes direct C/C++ support plus OpenGL ES and Vulkan via GLOVE middleware.
Tomi Engdahl says:
De-RISC Project Looks to Put the Free and Open RISC-V ISA in Satellites, Aircraft
Combining a RISC-V system-on-chip, multi-core interference mitigation technology and a smart hypervisor, De-RISC takes flight.
https://www.hackster.io/news/de-risc-project-looks-to-put-the-free-and-open-risc-v-isa-in-satellites-aircraft-24699411b6ef?9570efef719d705326f0ff817ef084e6
Tomi Engdahl says:
Internet of Things
SiFive is bringing RISC-V to IoT makers and university developers through the RISC-V-based SiFive Learn Initiative, an open-source learning package that can be used to create a low-cost RISC-V hardware compatible with AWS IoT Core. The development platform SiFive Learn Inventor has a software package and education enablement course. It includes:
The programmable SiFive Learn Inventor includes SiFive FE310 Processor with 150 Mhz clock speed, Bluetooth + Wi-Fi, an accelerometer, a gyroscope, a temperature sensor, a compass, an ambient light sensor, and a 6X8 display lights with 16M colors. SiFive also produces a board called SiFive Learn Inventor board, is available for preorder to use with the Inventor package.
https://semiengineering.com/week-in-review-iot-security-automotive-4/
https://www.prnewswire.com/news-releases/sifive-announces-sifive-learn-initiative-300967210.html
Tomi Engdahl says:
Microchip Makes has announced an early access program for its PolarFire SoC family of field-programmable gate arrays (FPGAs) — devices it is positioning as the first in the market to offer a hardened, real-time, Linux-compatible RISC-V microprocessor subsystem.
Microchip Opens Early Access Program for RISC-V-Powered Linux-Compatible PolarFire SoC FPGA
https://www.hackster.io/news/microchip-opens-early-access-program-for-risc-v-powered-linux-compatible-polarfire-soc-fpga-0aa207e3f80f
“The industry’s first RISC-V based SoC FPGA,” as Microchip positions it, is now available to “qualified customers.”
Tomi Engdahl says:
SiFive Launches Learn Inventor RISC-V Development Platform
https://www.hackster.io/news/sifive-launches-learn-inventor-risc-v-development-platform-0472f3d2218a
The SiFive Learn Inventor is a wireless RISC-V-based development kit inspired by the micro:bit.
Tomi Engdahl says:
SiFive unveiled two new product families. The SiFive Apex processor cores target mission-critical processors with Size, Weight, and Power (SWaP) optimization and are generated using the open-source Kami methodology. The SiFive Intelligence processor cores target deep learning markets with vector processing. It uses the RISC-V Vector Extension (RVV) and showed an average performance uplift of 9X vs traditional scalar processing on RISC-V.
https://semiengineering.com/week-in-review-design-low-power-73/
https://www.sifive.com/press/sifive-announces-new-technologies-for-mission-critical
Tomi Engdahl says:
Western Digital Corp. and Codasip are working together on Western Digital’s SweRV Core EH1, which is a RISC-V core with a 32-bit, dual superscalar, 9-stage pipeline architecture. The core, launched earlier this is aimed at embedded devices supporting data-intensive edge applications, such as storage controllers, industrial IoT, real-time analytics in surveillance systems, and other smart systems. Codasip is offering support package for SweRV, which includes components, tools and technical support.
https://semiengineering.com/week-in-review-iot-security-and-automotive/
https://codasip.com/2019/12/10/codasip-teams-up-with-western-digital-to-support-adoption-of-open-source-processors/
Tomi Engdahl says:
No batteries, no supercapacitors, no problem: ONiO claims its design can harvest power from the radio spectrum to operate at up to 24MHz.
ONiO.zero Offers Up to 24MHz of RISC-V Microcontroller Performance on Nothing But Harvested Energy
https://www.hackster.io/news/onio-zero-offers-up-to-24mhz-of-risc-v-microcontroller-performance-on-nothing-but-harvested-energy-70285321d50d
No batteries, no supercapacitors, no problem: ONiO claims its design can harvest power from the radio spectrum to operate at up to 24MHz
Norwegian healthcare-focused Internet of Things (IoT) specialist ONiO has unveiled ONiO.zero, an ultra-low-power RISC-V-based microcontroller capable of operating wholly from harvested energy — without needing a battery, capacitor, or any other form of energy storage.
“ONiO.zero is an ultra-low-power wireless MCU that uses energy harvesting technology,”
ONiO.zero is self-powered and supports a wide range of power sources from multi-frequency RF bands supporting GSM and ISM to optional external sources like solar, piezoelectric, thermal and voltaic cells.”
The microcontroller itself is based on the free and open source RISC-V instruction set architecture — specifically, RV32EMC — running at up to 24MHz when fed 1.8V. The controller also operates at lower voltages, when required: 1V gets you 6MHz, 0.8V gets you 1MHz, and the chip will continue to run – albeit at ever-decreasing speeds – as low as 450mV, the company claims. There’s 1kB of mask ROM and 2kB of RAM included, along with 8-32kB of ultra-low-power flash storage capable of 100,000 write cycles and readable down to 850mV.
The chip’s energy comes courtesy of an internal radio-frequency rectifier, harvesting power from the 800/900/1800 and 1900/2400MHz bands (ISM and GSM). For environments without enough radio-frequency energy to reliably power the chip, the “internal power factory” supports photovoltaic cells down to 400mV, piezoelectric, and thermal sources from 1.8V to 3.6V.
https://www.onio.com/technology.html
Tomi Engdahl says:
Creating a custom #processor with #RISCV #specialproject #opensource https://buff.ly/2ZhxYV7
Tomi Engdahl says:
Western Digital to Use RISC-V for Controllers, Processors, Purpose-Built Platforms
https://www.anandtech.com/show/12133/western-digital-to-develop-and-use-risc-v-for-controllers
Tomi Engdahl says:
Polos GD32VF103 Alef Brings 32-bit RISC-V Development Boards Below the $3 Mark
Breaking out all the GD32V’s features, AnalogLamb’s sub-$3 Polos GD32VF103 Alef offers low-cost entry into RISC-V development.
https://www.hackster.io/news/polos-gd32vf103-alef-brings-32-bit-risc-v-development-boards-below-the-3-mark-c073c33f2d0a
Tomi Engdahl says:
https://www.edn.com/creating-a-custom-processor-with-risc-v/
Tomi Engdahl says:
ONiO.zero Offers Up to 24MHz of RISC-V Microcontroller Performance on Nothing But Harvested Energy
https://www.hackster.io/news/onio-zero-offers-up-to-24mhz-of-risc-v-microcontroller-performance-on-nothing-but-harvested-energy-70285321d50d
No batteries, no supercapacitors, no problem: ONiO claims its design can harvest power from the radio spectrum to operate at up to 24MHz.
Tomi Engdahl says:
The SiFive Learn Inventor is a wireless RISC-V-based, AWS IoT Core-compatible dev kit inspired by the micro:bit.
SiFive Launches Learn Inventor RISC-V Development Platform
https://www.hackster.io/news/sifive-launches-learn-inventor-risc-v-development-platform-0472f3d2218a
The SiFive Learn Inventor is a wireless RISC-V-based development kit inspired by the micro:bit.
Tomi Engdahl says:
https://hackaday.com/2020/01/27/supercon-keynote-megan-wachs-breaks-down-risc-v/
Tomi Engdahl says:
RISC-V: Why The ISA Battles Aren’t Over Yet
https://hackaday.com/2019/11/12/risc-v-why-the-isa-battles-arent-over-yet/
Tomi Engdahl says:
https://hackaday.com/2019/11/19/emulating-risc-v-on-an-fpga/
Tomi Engdahl says:
The RISC-V Foundation, whose members include Qualcomm, NXP Semiconductors, and Huawei, recently moved its headquarters from the U.S. to Switzerland to ensure that universities, governments and companies outside the United States can maintain access to and develop the open-source RISC-processor core technology.
RISC-V To Move HQ to Switzerland Amid Trade War Concerns
https://www.eetimes.eu/risc-v-to-move-hq-to-switzerland-amid-trade-war-concerns/
Tomi Engdahl says:
Open source RISC-V architecture is changing the game for IoT processors
https://www.embedded-computing.com/guest-blogs/open-source-risc-v-architecture-is-changing-the-game-for-iot-processors
The Difference Between ARM, MIPS, x86, RISC-V And Others In Choosing A Processor Architecture
https://www.forbes.com/sites/tiriasresearch/2018/04/05/what-you-need-to-know-about-processor-architectures/amp/
Tomi Engdahl says:
Designed for both education and potential use in accelerators, RVSoC is portable and fully Linux-capable.
RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog
https://www.hackster.io/news/rvsoc-offers-a-lightweight-linux-capable-risc-v-core-in-just-5-000-lines-of-verilog-9a49976a6664
Designed for both education and potential use in accelerators, RVSoC is portable and fully Linux-capable.
A team from the School of Computing at the Tokyo Institute of Technology have developed a portable and Linux-capable RISC-V system-on-chip (SoC) design in just 5,000 lines of Verilog — and pledges to release it to all.
“RISC-V is an open and royalty free instruction set architecture which has been developed at the University of California, Berkeley. The processors using RISC-V can be designed and released freely,”
Tomi Engdahl says:
Ripes lets you code your own RISC-V processor, then see the program run in a fully interactive simulation.
Morten Petersen’s Ripes 2.0.0 Offers Interactive
https://www.hackster.io/news/morten-petersen-s-ripes-2-0-0-offers-interactive-visualization-and-simulation-of-risc-v-processors-eea1e92b3ed3
Visualization and Simulation of RISC-V Processors
Ripes lets you code your own RISC-V processor, then see the program run in a fully interactive simulation.
https://github.com/mortbopet/Ripes/releases
Tomi Engdahl says:
RVSoC Offers a Lightweight Linux-Capable RISC-V Core in Just 5,000 Lines of Verilog
https://www.hackster.io/news/rvsoc-offers-a-lightweight-linux-capable-risc-v-core-in-just-5-000-lines-of-verilog-9a49976a6664
Designed for both education and potential use in accelerators, RVSoC is portable and fully Linux-capable.
A team from the School of Computing at the Tokyo Institute of Technology has developed a portable and Linux-capable RISC-V system-on-chip (SoC) design in just 5,000 lines of Verilog — and pledges to release it to all.
“RISC-V is an open and royalty free instruction set architecture which has been developed at the University of California, Berkeley. The processors using RISC-V can be designed and released freely,”
Tomi Engdahl says:
Vortex Brings the RISC-V ISA to the World of OpenCL-Compatible General-Purpose GPUs
https://www.hackster.io/news/vortex-brings-the-risc-v-isa-to-the-world-of-opencl-compatible-general-purpose-gpus-389f8adc0f98
Evaluated at 15nm, the Vortex GPGPU and supporting software will be released as open source following blind review.
Tomi Engdahl says:
Espressif’s 240MHz ESP32-S2 SoCs, Modules, and Boards Enter Mass Production with RISC-V Coprocessor
https://www.hackster.io/news/espressif-s-240mhz-esp32-s2-socs-modules-and-boards-enter-mass-production-with-risc-v-coprocessor-9e70c98369dd
The ESP32-S2′s main 240MHz Xtensa LX7 CPU is joined by an ultra-low-power RISC-V coprocessor built into the RTC block.
Tomi Engdahl says:
Sipeed Brings Kendryte’s K210 Edge Neural Network Accelerator to PCIe M.2, USB Type-C with MAIX Nano
https://www.hackster.io/news/sipeed-brings-kendryte-s-k210-edge-neural-network-accelerator-to-pcie-m-2-usb-type-c-with-maix-nano-89aa85ef32c0
Available to pre-order now at just $9.90, the MAIX Nano M1n is a powerful dual-core RISC-V machine with dedicated NPU in a tiny form factor.
Tomi Engdahl says:
Sipeed MaixCube Brings RISC-V MicroPython to a Compact, Battery-Powered, All-in-One Form Factor
https://www.hackster.io/news/sipeed-maixcube-brings-risc-v-micropython-to-a-compact-battery-powered-all-in-one-form-factor-2095ce9b02a3
Built around Kendryte’s popular K210, the RISC-V MaixCube runs MicroPython but boasts support for the PlatformIO and Arduino IDEs too.
Tomi Engdahl says:
http://linuxgizmos.com/dev-kit-unlocks-secrets-of-1tops-kendryte-risc-v-chip/
Tomi Engdahl says:
RISC-V is an open source processor architecture that can be used in microprocessors, SOCs, and FPGA IP. It is revolutionizing the business model for deployment of architectures in the embedded systems marketplace. The RISC-V processor design is maturing rapidly, but RISC-V software enablement is in its infancy.
Tomi Engdahl says:
Sonal Pinto Recreates the Arduboy Using a Homebrew RISC-V SoC, the Kronos Zero Degree
The Kronos core, and the SoC which houses it, are open from the bottom up — and play Arduboy games brilliantly.
https://www.hackster.io/news/sonal-pinto-recreates-the-arduboy-using-a-homebrew-risc-v-soc-the-kronos-zero-degree-fc03046a1fdd
Tomi Engdahl says:
Development tools from IAR and Green Hills
https://www.uusiteknologia.fi/2020/06/03/uusia-kehitystyokaluja-risc-v-prosessoreille/
https://etn.fi/index.php/13-news/10834-avoin-mikro-ohjain-nopeasti-laitteisiin