Can RISC-V – Linux of Microprocessors – Start an Open Hardware Renaissance?

https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance

RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market? 

541 Comments

  1. Tomi Engdahl says:

    Yli tuhannen säikeen RISC-V-prosessori vaatii paljon
    https://etn.fi/index.php/13-news/14354-yli-tuhannen-saeikeen-risc-v-prosessori-vaatii-paljon

    MIPS on takavuosien iso nimi RISC-prosessoreissa ja nyt yhtiö siirtyy vauhdilla avoimeen Berkeleyn yliopistossa kehitettyyn RISC-V-arkkitehtuuriin. Yhtiö kehittää erittäin suorituskykyisiä prosessoreja, mikä vaatii paljon myös niiden verifioinnilta eli toiminnallisuuden varmentamiselta.

    MIPS kertoo nyt, että se on valinnut Imperas Softwaren työkalut omien RISC-V-suunnittelujensa verifiointiin. Imperasin työkalut tukevat menetelmiä, joilla siirrytään saumattomasti ongelmien havaitsemisen ja virheenkorjauksen välillä yhtenäisessä testipenkkiympäristössä, joka on yhteensopiva johtavien SystemVerilog-pohjaisten EDA -työkalujen kanssa.

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  2. Tomi Engdahl says:

    MIPS has announced the launch of its first processor core based on the free and open source RISC-V instruction set architecture, the eVocore P8700 Multiprocessor — capable of scaling up to 512 cores and claimed to offer higher single-threaded performance than rival designs.

    MIPS Launches Its First RISC-V Design, the High-Performance eVocore P8700 Multiprocessor
    https://www.hackster.io/news/mips-launches-its-first-risc-v-design-the-high-performance-evocore-p8700-multiprocessor-f53a363bf2f0

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  3. Tomi Engdahl says:

    XMOS has announced its next-generation xcore processor platform — in which it’s breaking with tradition and taking a leaf from the free and open source RISC-V ISA, making something it says is a “RISC-V compatible architecture.”

    XMOS Adopts RISC-V for Next-Generation xcore Software-Defined Systems-on-Chips
    https://www.hackster.io/news/xmos-adopts-risc-v-for-next-generation-xcore-software-defined-systems-on-chips-0426dc4dd7f3?fc56459a18776e2a100854c16a1fd78b

    Intelligent Internet of Things (IoT) company the latest to jump on the free and open source RISC-V ISA bandwagon, starting in 2023.

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  4. Tomi Engdahl says:

    Ensimmäinen kaupallinen Linux tuli RISC-V-piireille
    https://etn.fi/index.php/13-news/14376-ensimmaeinen-kaupallinen-linux-tuli-risc-v-piireille

    Siemensin Digital Industries Software ilmoittaa, että sen Sokol Flex OS -ohjelmisto tukee nyt RISC-V-ppohjaista sulautettua kehitystä. Samalla Sokol Flex OS:stä tulee ensimmäinen kaupallisesti tuettu Linux-alusta Berkeleyn yliopistossa kehitetylle viiden polven avoimelle prosessoriarkkitehtuurille.

    Sokol Flex OS perustuu suosittuun avoimen lähdekoodin Yocto-standardiin, ja se auttaa sulautettuja kehittäjiä luomaan räätälöityjä Linux-pohjaisia järjestelmiä RISC-V-arkkitehtuureille helposti, turvallisesti ja luotettavasti. RISC-V-arkkitehtuuri sopii ihanteellisesti teollisuus-, lääketieteellinen-, puolustus- ja ilmailu- ja kuluttajasovelluksiin. Semico Research ennustaa, että vuoteen 2025 mennessä markkinoille tulee 62,4 miljardia RISC-V-ydintä laajassa valikoimassa erilaisia sovelluksia.

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  5. Tomi Engdahl says:

    Charles Lohr’s Linux-Capable Really Tiny RISC-V Emulator Exists in a Single 400-Line C Header File
    Existing in a single 400-line header file, this RISC-V emulator can boot a usable Linux operating system and run executables.
    https://www.hackster.io/news/charles-lohr-s-linux-capable-really-tiny-risc-v-emulator-exists-in-a-single-400-line-c-header-file-7d7801cf042c

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  6. Tomi Engdahl says:

    Integrity FASTApps from Breker is a library of automated test-generation IP elements that provides high-coverage verification for RISC-V processor cores and SoCs….

    https://www.edn.com/test-generation-library-verifies-risc-v-processors/

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  7. Tomi Engdahl says:

    https://etn.fi/index.php/13-news/14400-risc-v-tuli-fpga-piireille

    Microchip on jo toimittanut ensimmäiset FPGA-piirinsä, joilta RISC-V-prosessori löytyy. Kyse on logiikkakapasiteetilla mitattuna keskiluokan siruista, joilla RISC-V on tuonut kaksi kertaa enemmän tehoa kuin kilpailevilla keskitason FPGA-piireillä.

    Microchipille ohjelmoitavat kenttämatriisipiirit tulivat Microsemi-ostoksen myötä 4,5 vuotta sitten. RISC-V Summitissa yhtiö esitteli uusia PolarFire 2 -sarjan piirejä ja sille kehitettyä RISC-V-pohjaista prosessorialijärjestelmää ja ohjelmistopakettia.

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  8. Tomi Engdahl says:

    New Dev Platforms Bring RISC-V to the Forefront of Innovation (Part 1)
    Dec. 6, 2022
    More companies are on track to adopt the RISC-V architecture for new applications that range from robotics to home automation.
    https://www.electronicdesign.com/technologies/embedded-revolution/media-gallery/21255925/electronic-design-new-dev-platforms-bring-riscv-to-the-forefront-of-innovation-part-1

    What you’ll learn:

    What is RISC-V?
    What are some of the popular RISC-V platforms for development?

    New Dev Platforms Bring RISC-V to the Forefront of Innovation (Part 2)
    Dec. 15, 2022
    Part 2 looks at more companies that are on track to adopt the RISC-V architecture for new applications ranging from robotics to home automation.
    https://www.electronicdesign.com/technologies/embedded-revolution/media-gallery/21256497/electronic-design-new-dev-platforms-bring-riscv-to-the-forefront-of-innovation-part-2

    What you’ll learn:

    What is RISC-V?
    What are some of the popular RISC-V platforms for development?

    Reply
  9. Tomi Engdahl says:

    The Efinity RISC-V Embedded Software IDE from Efinix is an Eclipse-based integrated development environment (IDE) powered by Ashling’s RiscFree IDE….

    https://www.edn.com/development-environment-builds-risc-v-code/

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  10. Tomi Engdahl says:

    Bouffalo Lab BL616/BL618 RISC-V MCU supports WiFi 6, Bluetooth 5.2, and Zigbee
    Bouffalo Lab BL616/BL618 is a 32-bit RISC-V wireless microcontroller with support for 2.4 GHz WiFi 6, Bluetooth 5.2 dual-mode, and an 802.15.4 radio for Zigbee, Thread, and Matter designed for IoT applications.
    https://www.cnx-software.com/2022/12/29/bouffalo-lab-bl616-bl618-risc-v-mcu-wifi-6-bluetooth-5-2-zigbee/

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  11. Tomi Engdahl says:

    Ron Amadeo / Ars Technica:
    Android’s director of engineering said Google wants RISC-V as a “tier-1” Android architecture and shared a years-long roadmap at December 2022′s RISC-V summit — Google’s keynote at the RISC-V Summit promises official, polished support. — Over the holiday break …

    Google wants RISC-V to be a “tier-1” Android architecture
    Google’s keynote at the RISC-V Summit promises official, polished support.
    https://arstechnica.com/gadgets/2023/01/google-announces-official-android-support-for-risc-v/

    Over the holiday break, the footage from the recent “RISC-V Summit” was posted for the world to see, and would you believe that Google showed up to profess its love for the up-and-coming CPU architecture?

    We’ve been trying to nail down how the Android team feels about RISC-V (reduced instruction set computer) for a while. We last heard a comment from the team six months ago, where our Google I/O question about RISC-V was answered only with “we’re watching, but it would be a big change for us.” Some external RISC-V porting projects exist, and various RISC-V commits have been landing in the Android Open Source Project (AOSP), but since anyone can submit code to AOSP, it has been hard to make any bold proclamations about RISC-V’s Android status.

    Google’s keynote at the RISC-V Summit was all about bold proclamations, though. Lars Bergstrom, Android’s director of engineering, wants RISC-V to be seen as a “tier-1 platform” in Android, which would put it on par with Arm. That’s a big change from just six months ago. Bergstrom says getting optimized Android builds on RISC-V will take “a lot of work” and outlined a roadmap that will take “a few years” to come to fruition, but AOSP started to land official RISC-V patches back in September.

    The build system is up and running, and anyone can grab the latest “riscv64″ branch whenever they want—and yes, in line with its recent Arm work, Google wants RISC-V on Android to be 64-bit only. For now, the most you can get is a command line, and Bergstrom’s slide promised “initial emulator support by the start of 2023, with Android RunTime (ART) support for Java workloads following during Q1.”

    One of Bergstrom’s slides featured the above “to-do” list, which included a ton of major Android components. Unlike Android’s unpolished support for x86, Bergstrom promised a real push for quality with RISC-V, saying, “We need to do all of the work to move from a prototype and something that runs to something that’s really singing—that’s showing off the best-in-class processors that [RISC-V International Chairman Krste Asanović] was mentioning in the previous talk.”

    Once Google does get Android up and running on RISC-V, then it will be up to manufacturers and the app ecosystem to back the platform. What’s fun about the Android RunTime is that when ART supports RISC-V, a big chunk of the Android app ecosystem will come with it.

    Arm has become an unstable, volatile business partner

    In her opening remarks, RISC-V International (the nonprofit company that owns the architecture) CEO Calista Redmond argued that “RISC-V is inevitable” thanks to the open business model and wave of open chip design that it can create, and it’s getting hard to argue against that. While the show was mostly about the advantages of RISC-V, I want to add that the biggest reason RISC-V seems inevitable is that current CPU front-runner Arm has become an unstable, volatile company, and it feels like any viable alternative would have a good shot at success right now.

    The world’s biggest companies are building trillion-dollar businesses on top of the Arm architecture, and the realities of product design mean all these plans are two to five years out. So for Arm, giving off a vibe of “instability” is probably the single biggest thing it can do to drive away customers. It would be great if Arm chips are cheap and fast and have a great ecosystem, but before any of that matters, customers need to be confident in the company’s future. When Arm regularly spent the last three years lighting up the tech news headlines, can anyone say where the company will be in five years? Arm’s licensing model traditionally made it a stable, neutral, reliable company, and for customers, it’s probably completely unacceptable that Arm is acting like this.

    The other reason to kick Arm to the curb is the US-China trade war, specifically that Chinese companies (and the Chinese government) would really like to distance themselves from Western technology. 2019 and 2020 saw the US government systematically destroy one of China’s largest tech companies, Huawei, with trade sanctions. One of the biggest weapons used was Arm, which was forced to cut off its relationship with Huawei for several months. Arm—technically a UK company under the ownership of a Japanese investment firm—originally decided its designs were subject to US export law, then decided they were not, and recently decided that some chips actually are again. The up-and-down relationship has resulted in months of disruption for Huawei’s business and future plans. Coupled with losing access to chip fabs like TSMC, Huawei’s market share has tanked, and the company is now in “survival mode.”

    RISC-V is seen as a way to be less reliant on the West. While the project started at UC Berkeley, RISC-V International says the open source architecture is not subject to US export law. In 2019, the RISC-V Foundation actually moved from the US to Switzerland and became “RISC-V International,” all to try to avoid picking a side in the US-China trade war. The result is that Chinese tech companies are rallying around RISC-V as the future chip architecture. One Chinese company hit by US export restrictions, the e-commerce giant Alibaba, has been the leading force in bringing RISC-V support to Android, and with Chinese companies playing a huge part in the Android ecosystem, it makes sense that Google would throw open the doors for official support. Now we just need someone to build a phone.

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  12. Tomi Engdahl says:

    Espressif Systems has added a new system-on-chip to the ESP32 family. The RISC V-based ESP32-P4 has three cores, 50 programmable GPIO, and a complete set of security features. But, curiously, the chip is missing one feature synonymous with “Espressif SoC:” an RF radio!

    Espressif’s New High-Performance RISC-V ESP32-P4 SoC Packs in Tons of IO and Security Features
    … but it does not have any wireless connectivity.
    https://www.hackster.io/news/espressif-s-new-high-performance-risc-v-esp32-p4-soc-packs-in-tons-of-io-and-security-features-12272d4b067e

    ESP32-P4′s high-performance CPU is a dual-core RISC-V CPU running up to 400 MHz. It has 768 kilobytes of on-chip SRAM. But, if you add an external PSRAM, the on-chip RAM becomes a local cache. There are also eight kilobytes of zero-wait tightly coupled memory (TCM) for low latency buffer access.

    The low-power system is a single RISC-V core running up to 40 MHz with dedicated SRAM, ROM, and peripherals. It also houses the SoC’s power management unit (PMU). Its peripherals include low-speed serial interfaces, a touch interface, and a temperature sensor.

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  13. Tomi Engdahl says:

    Written in RISC-V assembly, this tiny Forth port is open source and fully functional on the Longan Nano microcontroller.

    Alexander Williams’ FiveForths Is a “Hand-Written” RISC-V Assembly Forth for Microcontrollers
    https://www.hackster.io/news/alexander-williams-fiveforths-is-a-hand-written-risc-v-assembly-forth-for-microcontrollers-573b5f0ed9f8

    Written in RISC-V assembly, this tiny Forth port is open source and fully functional on the Longan Nano microcontroller.

    Developer Alexander Williams has written and released a “tiny hand-written” port of the Forth programming language to the low-cost Longan Nano RISC-V microcontroller, using only RISC-V assembly — and it’s called FiveForths.

    First released in 1970 by Charles H. Moore, Forth is a stack-oriented programming language that failed to make inroads in the early home computing market against rival BASIC but which found itself a niche in the embedded sector

    The project is notable for having been hand-crafted in RISC-V assembly, and for its compact size — ideal for microcontroller use, where resources are typically constrained. The source code is available on GitHub under the permissive MIT license, while Williams has penned a series of “Devlogs” covering major milestones in the project on the FiveForths website.

    https://github.com/aw/fiveforths

    https://aw.github.io/fiveforths/

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  14. Tomi Engdahl says:

    64-bit RISC-V Microprocessor Delivers New Options for IoT Edge Development
    https://www.renesas.com/eu/en/document/whp/64-bit-risc-v-microprocessor-delivers-new-options-iot-edge-development

    Global and rapidly expanding IoT edge devices are becoming increasingly important for connecting various
    sensors to the cloud via networks. IoT edge devices are progressively integrating 64-bit microprocessors
    capable of running Linux and similar high-performance operating systems. Moreover, recent import and
    export regulation changes have produced a need for choices in CPU architecture for microprocessors to
    generate a stable supply of IoT devices. The RZ/Five boasts multiple features which help resolve these
    issues.

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  15. Tomi Engdahl says:

    Android tulee RISC-V-piireille
    https://etn.fi/index.php/13-news/14462-android-tulee-risc-v-piireille

    Berkeleyn yliopistossa kehitetty RISC-V-käskykanta on saavuttanut suurta suosiota sulautetuissa sovelluksissa ja sitä viedään myös PC-luokan prosessoreihin vauhdilla. Seuraavaksi ovat vuorossa älypuhelimet. Google ilmoitti jo tuovansa Androidiin tuen arkkitehtuurille.

    Tällä hetkellä Android tukee kahta laitealustaa: Arm ja X86. Joulukuussa Google ilmoitti RISC-V Summitissa, että Androidin avoimeen versioon (AOSP) lisätään tuki RISC-V-käskyille. Toki vain 64-bittisenä, sillä puhelimissa ollaan siirtymässä pois vanhasta 32-bittisestä maailmasta.

    Google mukaan projekti vie aikaa. Se alkaa RISC-V-tuen tuomisella Android-ajoympäristöön, mikä voisi tapahtua jo tänä vuonna. Android on pitkälti javaa: käyttöliittymät, iso osa järjestelmäpalveluista jne. on toteutettu javalla. Näin ollen hanke saada Android toimimaan RISC-V:llä ei ole mitenkään mahdotonta.

    Iso kysymys on tietenkin miksi? Vstaus on varsin yksinkertainen. Avointa RISC-V-arkkitehtuuria voi kuka tahansa käyttää ilman lisenssejä ja rojaltimaksuja. Arm-piirien käyttäminen älypuhelimissa maksaa, ja Qualcomm ja Mediatekin kaltaiset valmistajat maksavat Arm:lle isoja summia oikeudesta käyttää käskykantaa. Potentiaalisesti RISC-V-älypuhelimet olisivat siis edullisempia.

    Sen jälkeen kysymys on siitä, haluaisivatko kuluttajat uudenlaisia Android-puhelimia.

    AndroidAuthority-sivusto kysyi asiaa lukijoiltaan ja tulos on varsin vaikuttava. Lähes 46 prosenttia ostaisi RISC-V-puhelimen ja yli toiset 51 prosenttia ostaisi, jos suorituskyky olisi nykyisten laitteiden tasolla.

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  16. Tomi Engdahl says:

    EEVblog 1524 – The 10 CENT RISC V Processor! CH32V003
    https://www.youtube.com/watch?v=L9Wrv7nW-S8

    Checking out the new 10 cent WCH CH32V003 48MHz RISC V processor demo board and the MounRiver Eclipse IDE. Getting to blinky.
    The CH32V003 is a pin-for-pin alternative to the STM8S003 at 1/3rd the price, with more features.

    00:00 – WCH CH32V003 RISC V Processor
    02:01 – CH32V003F4P6 Eval board
    03:00 – Pin-for-pin replacement for the ST STM8S003
    04:30 – Datasheet and reference manual
    05:24 – MounRiver Eclipse IDE
    07:13 – It just worked
    10:58 – Open Source GNU RISC V Cross Compiler
    11:38 – Download and flash a LED, maybe…
    13:51 – Save the file first, dummy.
    15:26 – All the includes and headers
    17:37 – But can you buy them?
    18:11 – How fast can the pin toggle?

    https://www.eevblog.com/forum/blog/eevblog-1524-the-10-cent-risc-v-processor-ch32v003/

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  17. Tomi Engdahl says:

    POSTED ONJANUARY 16, 2023 BY JEAN-LUC AUFRANC (CNXSOFT) – 7 COMMENTSON $4 SIPEED M0S DOCK IOT DEVELOPMENT BOARD FEATURES BL616 WIFI 6, BLE 5.2, AND ZIGBEE RISC-V MICROCONTROLLER
    $4 Sipeed M0S Dock IoT development board features BL616 WiFi 6, BLE 5.2, and Zigbee RISC-V microcontroller
    https://www.cnx-software.com/2023/01/16/4-sipeed-m0s-dock-iot-development-board-bl616-wifi-6-ble-5-2-and-zigbee-risc-v-microcontroller/

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  18. Tomi Engdahl says:

    Huonoja uutisia Arm- ja X86-piireille
    https://etn.fi/index.php/13-news/14475-huonoja-uutisia-arm-ja-x86-piireille

    Berkeleyn yliopistossa kehitetty avoin RISC-V-arkkitehtuuri on saavuttanut lyhyessä ajassa paljon suosiota, mutta tämä on vasta alkua. Joulukuussa järjestetyssä RISC-V_ Summit -tapahtumassa RISC-V Internationalin toimitusjohtaja Calista Redmond hehkutti, että RISC.Vn voitto on lopulta väistämätöntä.

    - Avoin arkkitehtuuri mahdollistaa parhaat prosessorit, parhaat suorittimilla toimivat ohjelmistot ja parhaan ekosysteemin, Redmond sanoi. Tätä hän perusteli sillä, että niin moni yritys, yliopisto ja tutkimuslaitos panostaa alustan kehittämiseen.

    Markkinoilla on jo yli 10 miljardia RISC-V-arkkitehtuuriin pohjautuvaa prosessoria. Sitä käytetään jo alhaisen virrankulutuksen IoT-laitteiss,a mutta myös parasta suorituskykyä vaativissa laitteissa.

    - RISC-V on kehitetty ohjelmistovetoisesti modulaariseksi alustaksi. Tämä antaa suunnittelijoilla paljon vapauksia, Redmond hehkutti.

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  19. Tomi Engdahl says:

    SiFive has revealed additional details about its upcoming HiFive Pro P550 single-board computer, a desktop-class device built in partnership with Intel, which the companies hope will become the go-to gadget for RISC-V development.

    SiFive’s HiFive Pro P550, Developed in Partnership with Intel, Aims to Be the Fastest RISC-V SBC Yet
    https://www.hackster.io/news/sifive-s-hifive-pro-p550-developed-in-partnership-with-intel-aims-to-be-the-fastest-risc-v-sbc-yet-5789a4734bcc

    “RISC-V is inevitable,” the company claims, as it partners with x86 giant Intel to release its quad-core 64-bit micro-ATX dev board.

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  20. Tomi Engdahl says:

    Selecting The Right RISC-V Core
    https://semiengineering.com/selecting-the-right-risc-v-core/

    facebook sharing button 84sharethis sharing button
    Ensuring that your product contains the best RISC-V processor core is not an easy decisio

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  21. Tomi Engdahl says:

    Arbitrary Precision DNN Accelerator Controlled By A RISC-V CPU (Ecole Polytechnique Montreal, IBM, Mila, CMC)
    https://semiengineering.com/arbitrary-precision-dnn-accelerator-controlled-by-a-risc-v-cpu-ecole-polytechnique-montreal-ibm-mila-cmc/

    A new technical paper titled “BARVINN: Arbitrary Precision DNN Accelerator Controlled by a RISC-V CPU” was written by researchers at Ecole Polytechnique Montreal, IBM, Mila and CMC Microsystems. It was accepted for publication in the 2023, 28th Asia and South Pacific Design Automation Conference (ASP-DAC 2023) in Japan.

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  22. Tomi Engdahl says:

    https://etn.fi/index.php/13-news/14502-kiinalainen-risc-v-ohjain-kiihdytti-jo-gigahertsiin

    Kiinalainen Xianji Semiconductor on esitellyt avoimeen RISC-V-arkkitehtuuriin perustuvan ohjainpiirin, jonka kellotaajuus on saatu nostettua jo yhteen gigahertsiin. Piirit valmistetaan 40 nanometrin prosessissa.

    HPM64G0-ohjain seuraa viime marraskuussa julkistettuja HPM6700/6400 -sarjan ohjaimia. Verrattuna muihin aiemmin julkaistuihin HPM6700/6400-sarjan MCU-tuotteisiin HPM64G0:n laskentasuorituskyky on parantunut 20 prosenttia. Kyse on merkittävästä saavutuksesta, sillä kasvaneen tehon myötä avoimella ohjainpiirillä voidaan ajaa reaaliaikaisia prosesseja.

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  23. Tomi Engdahl says:

    Frederic Lardinois / TechCrunch:
    Google previews features for its open-source multiplatform UI framework Flutter, like RISC-V support and easier embedding of Flutter code into existing apps

    Google’s Flutter showcases new graphics capabilities, WebAssembly and RISC-V support
    https://techcrunch.com/2023/01/25/googles-flutter-showcases-new-graphics-capabilities-webassembly-and-risc-v-support/

    Flutter, Google’s open-source framework for building multi-platform apps for mobile, web and desktop, is hosting its Flutter Forward event in Nairobi, Kenya today. As the name implies, the team is using the event to showcase up-and-coming features of the framework — most of which are still very early in their development cycle. The main highlights here are massively improved graphics performance, the ability to more easily embed Flutter code into existing web and mobile apps, and support for new architectures like Web Assembly and RISC-V. Virtually all of these capabilities still sit in canary branches and behind experiment flags, but they do show where Google plans to take this project in the months ahead — and help the overall open-source ecosystem around it understand where some complimentary work could be useful (about 40% of contributors to Flutter are outside of Google).

    To enable this performance, the engine now features pre-compiled shaders, avoiding the frame drops of the previous engine during shader compilation. There’s also now support for custom shaders and pixel shaders, which enables a number of new effects — which in turn will enable developers to build a host of new experiences on top of Flutter. Underneath all of this sit the low-level Vulkan and Metal 3D graphics APIs of Android and iOS. Currently, the team is focusing its work here on mobile, though many of these new graphics capabilities should also work on macOS and Windows already. “Our general model for Flutter is take it everywhere you can paint pixels,” Sneath said.

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  24. Tomi Engdahl says:

    From Siemens:

    “As we welcome a new year, we continue seeing solid RISC-V adoption from SoC designers and architects. RISC-V will play a critical role in driving the development of more innovative and efficient chips and allowing companies to get to market faster. With our recent release of Nucleus, we have become the leading RTOS vendor supporting RISC-V. Learn more about the advanced features supporting RISC-V, such as simplified debug and development tool integration and Nucleus symmetric multi-processing with auto-load balancing and task affinity for optimal deterministic operation in this new video RISC-V Support in Nucleus 4.1.0″

    RISC-V Support in Nucleus 4.1.0
    https://resources.sw.siemens.com/en-US/technology-overview-riscv-support-nucleus?utm_campaign=2023-1-global-eda_siemens_embedded_january_nl&utm_source=ema&utm_medium=email

    With the 4.1.0 release, Nucleus becomes the leading RTOS vendor now supporting RISC-V. Learn more about the advanced features supported in this latest release of Nucleus RTOS.

    Reply
  25. Tomi Engdahl says:

    RISC-V-based chips are turning up in everything from laptops to autonomous car systems.

    An open-source option is shaking up the microchip industry
    https://www.freethink.com/hard-tech/risc-v?utm_source=facebook&utm_medium=social&utm_campaign=BigThinkdotcom

    RISC-V-based chips are turning up in everything from laptops to autonomous car systems.

    Reply
  26. Tomi Engdahl says:

    HiFive Pro P550 “Horse Creek” RISC-V motherboard with 16GB RAM to launch this summer
    https://www.cnx-software.com/2023/01/24/hifive-pro-p550-horse-creek-risc-v-sbc16gb-ram/

    SiFive HiFive Pro P550 RISC-V motherboard based on Intel “Horse Creek” quad-core SiFive Performance P550 processor will launch this summer with 16GB DDR5 memory, two PCIe expansion slots, Gigabit Ethernet networking, USB 3.x ports, and on-board graphics.

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  27. Tomi Engdahl says:

    An open-source option is shaking up the microchip industry
    RISC-V-based chips are turning up in everything from laptops to autonomous car systems.
    https://www.freethink.com/hard-tech/risc-v

    Reply

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