https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance
RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market?
655 Comments
Tomi Engdahl says:
Karl Freund / Forbes:
Intel announces efforts to accelerate RISC-V development and adoption, including licensing plans, chip manufacturing partners, and a $1B IFS Innovation Fund — This announcement will have a long-lasting impact on the entire semiconductor industry: — Intel must fabricate chips …
Intel Creates $1B Innovation Fund To Grow RISC-V Market (And Attract New Foundry Customers)
https://www.forbes.com/sites/karlfreund/2022/02/07/intel-creates-1b-innovation-fund-to-grow-risc-v-market-and-attract-new-foundry-customers/?sh=5912eb1616aa
This announcement will have a long-lasting impact on the entire semiconductor industry:
Intel must fabricate chips for its competitors to grow its foundry business, and is investing in the emerging RISC-V market as the catalyst.
Intel competitors Andes Technology, Esperanto Technologies, SiFive and Ventana Micro are now early partners.
Back in 2006, Intel decided to abandon the company’s Arm-based CPU development project, selling the XScale PXA technology to Marvell Technology Group for some $600M. The thinking then was that the x86 architecture would form the cornerstone of all Intel processor designs, a strategy which served the company well for over a decade. But now, Intel sees increasing competition from AMD as well as Arm-based chips from scores of companies, and needs more customers to fill its multi-billion dollar fab facilities.
Consequently, Intel must become a preferred manufacturing partner for chips that will directly compete with Intels own products. RISC-V designers are knocking on the door to find more fab capacity, and Intel decided to answer with a big welcome sign with a B on it.
From Intel’s perspective, embracing RISC-V, along with x86 and Arm, helps the Intel Foundry Services business become a new option for fabless semiconductor companies to consider, along with TSMC, Samsung, and Global Foundries. From the perspective of other chip vendors, Intel could represent a white knight in a world of tight fab capacity, providing needed capital, fab services, and valuable technology that could help them get ahead. This will take time to materialize, but today’s announcement will lay the foundation. Companies needing access to advanced process nodes, such as 3 and 5 nm, really have nowhere to go; TSMC and Samsung advanced node capacity is essentially sold out just supplying chips to Apple, NVIDIA, and Qualcomm.
What did Intel Announce?
In a slew of announcements, Intel made it clear that it will remake itself in order to remain the #1 US semiconductor fabricator , and that it will become more open in order to fill new facilities under construction in Arizona and now in Ohio. And that shift will grow market share.
Key elements of Intel’s IFS Innovation Fund announcement include:
A $1B IFS Innovation Fund to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem. A large part of this will be to accelerate RISC-V.
Intel is joining RISC-V International, the governing consortium that guides the RISC-V technology and community.
Intel announced partners that will manufacture future RISC-V chips on IFS technologies, including those from Andes, Esperanto, and Ventana.
Intel will license differentiated RISC-V IP to accelerate innovation.
Intel will provide access to open Intel Chiplet building blocks based on RISC-V, leveraging advanced packaging and high-speed chip-to-chip interfaces.
Intel also mentioned that they will be supporting design approaches that will support multiple instruction architectures including x86, Arm, and RISC-V. So, they appear to want to become the Switzerland of Fab Services.
Intel also announced the IFS Accelerator, an alliance to provide access to design services, IP, and tools and flows to enable development of next-generation customer products. So Intel won’t just be a fab, they will be a leading-edge service provider to the industry.
RISC-V: The anti-Arm
Open-source RISC-V cores are becoming the go-to technology for many devices, from low-end embedded controllers and more recently to high-performance AI chips from Esperanto for AI and Ventana Micro for servers. Despite these two exceptions, the lack of a robust ecosystem has limited the open-source technology primarily to embedded devices such as those from Andes Technology, where the license-free cores provide competitive performance as an alternative to Arm. Intel’s billion dollar investment is unprecedented, and will potentially reshape the industry landscape. The timing couldn’t be better, as the potential sale of Arm to NVIDIA, which has recently been shelved, spurred many developers to search for an alternative to Arm technology, and RISC-V is that technology.
System on a Package
Many cloud service providers as well as startups are designing multi-chiplet platforms for workloads such as AI, placing accelerators, CPUs, and I/O dies (possibly from different manufacturing nodes) on a package. “System on a Package” is the new mantra, but there are few companies that have the required technology and available fabrication capacity to make it real. In the old days, Intel saved the underlying technologies such as EMIB for multi-die packages as a differentiator for Intel products. Now Intel is stepping up and making this approach available for all comers. Is Intel becoming Open? Sounds like it to me.
Tomi Engdahl says:
Suoritinvalmistaja Intel liittyy mukaan RISC-V Internationaliin. Tämä povaa tietä tulevaisuudelle, jossa maailmassa on kolme merkittävää siruarkkitehtuuria: ARM, x86-64 ja RISC-V.
Intel joins RISC-V International and Invests Another Billion in Foundry
https://www.servethehome.com/intel-joins-risc-v-international-and-invests-another-billion-in-foundry-esperanto/
Tomi Engdahl says:
Intel joins RISC-V governing body, pledges $1bn fund for chip designers
Now that’s a shot in the Arm
https://www.theregister.com/2022/02/07/intel_riscv_investment/
Tomi Engdahl says:
Code size: Closing the gap between RISC-V and Arm for embedded applications
https://blog.segger.com/code-size-closing-the-gap-between-risc-v-and-arm-for-embedded-applications/
One of the issues faced by RISC-V developers is that the code density of the RISC-V instruction set for deeply embedded processors does not match that of Cortex-M with existing tools. That is changing with the product innovations SEGGER have developed, such as the recently-announced SEGGER Linker, capable of reducing code size by up to 15%, and the SEGGER Runtime Library, performance and size optimized for RISC-V.
Tomi Engdahl says:
The debate is getting hotter and hotter: ARM or RISC-V? ARM and RISC-V? Are ARM and RISC-V competitors or synergic?
https://www.e4company.com/en/2021/09/the-debate-is-getting-hotter-and-hotter-arm-or-risc-v-arm-and-risc-v-are-arm-and-risc-v-competitors-or-synergic/
When talking about processors, the most important factor to consider is the instruction set architecture, or ISA. This is because programs developed by software engineers will only be able to operate on specifics ISAs unless the code is written using an interpreted language that is cross-platform (such as Python or Java). There are many ISAs available to designers. With regards to large processing systems such as HPC systems and clusters, the two ISAs most widely used are x86/x64 and ARM.
ARM is the most successful RISC architecture on the planet, with its licensees shipping billions of chips a year and is the dominant CPU architecture for microcontrollers, microprocessors, and mobile systems, and is increasing its footprint in HPC.
While x86/x64 and ARM are the dominant architecture in the heavy processing market, they may face serious competition from a new processor architecture: RISC-V.
Emerging in 2010 from the Parallel Computing Lab at UC Berkeley in California, RISC-V is a modular architecture that allows developers to build whatever they desire on top of the core instruction set.
Tomi Engdahl says:
https://www.tomshardware.com/news/intel-1b-fund-risc-v
Tomi Engdahl says:
https://www.servethehome.com/intel-joins-risc-v-international-and-invests-another-billion-in-foundry-esperanto/
Tomi Engdahl says:
The debate is getting hotter and hotter: ARM or RISC-V? ARM and RISC-V? Are ARM and RISC-V competitors or synergic?
https://www.e4company.com/en/2021/09/the-debate-is-getting-hotter-and-hotter-arm-or-risc-v-arm-and-risc-v-are-arm-and-risc-v-competitors-or-synergic/
Tomi Engdahl says:
RISC-V or Arm? This tiny 4x4cm Linux board with WiFi offers both options
https://www.cnx-software.com/2022/02/13/arm-or-risc-v-mangopi-mq-tiny-4x4cm-linux-board-with-wifi/
Last fall, we wrote about Allwinner D1s/F133-A RISC-V processor and the upcoming MangoPi MQ1, a tiny 4x4cm board based on the processor. The board is not for sale, but we have more details, and the company is also working on an Arm version equipped with Allwinner T113-S3 dual-core Cortex-A7 processor that is pin-to-pin compatible with F133-A SoC.
Tomi Engdahl says:
SoC (one or the other)
MangoPi MQ – Allwinner D1s/F133-A 64-bit RISC-V processor @ 1 GHz with 64 MB DDR2
MangoPi MQ-Dual – Allwinner T113-S3 32-bit dual-core Arm Cortex-A7 processor with 128 MB DDR3
https://www.cnx-software.com/2022/02/13/arm-or-risc-v-mangopi-mq-tiny-4x4cm-linux-board-with-wifi/
Tomi Engdahl says:
RISC-V nousee x86:n ja Arm-arkkitehtuurin rinnalle
https://etn.fi/index.php/13-news/13168-risc-v-nousee-x86-n-ja-arm-arkkitehtuurin-rinnalle
Laskenta on tällä hetkellä jakautunut sulautettujen Arm-suorittimien ja tietokoneiden x86-piirien välillä. Nyt on paljon merkkejä siitä, että avoin RISC-V-arkkitehtuuri nousee kahden valtavirran rinnalle sekä sulautetuissa että tietokoneissa.
Viime viikolla Intel yllätti monet liittymällä RISC-V International -järjestöön premium-tason jäseneksi. Intel aikoo tarjota laitevalmistajille sopimusvalmistusta, jossa prosessoriarkkitehtuurin saa valita kolmesta mahdollisesta.
Intel ottaa RISC-V:n tosissaan. Yhtiön valmistuspalveluista vastaavan Randhir Thakurin mukaan yhtiö haluaa rakentaa RISC-V-ekosysteemin yhdessä prosessoreita kehittäneiden pioneerien kuten SiFIve kanssa. Ohjelmistotyökaluihin ja kotelointiratkaisuihin Intel aikoo panostaa miljardi dollaria oman Intel Capital -pääomayrityksen kanssa.
Viime viikolla kuultiin myös, että Nvidia luopui aikeistaan ostaa Arm japanilaiselta Softbankilta. Nykyisten Arm-lisensoijien asemaa uhanneen kaupan sijaan Arm viedään nyt pörssiin. Analyytikoiden mukaan kaupan peruuntuminen saattaa kuitenkin tehdä RISC-V:stä vieläkin houkuttelevamman vaihtoehdon Arm-piireille.
Tomi Engdahl says:
A Big Week for RISC-V
https://www.eetimes.com/a-big-week-for-risc-v/
It’s been a banner week for the RISC-V ecosystem. The profile of the open-source instruction set architecture (ISA) has been raised by a pair of announcements. Let’s take a closer look.
Intel support
Earlier this week, Intel announced it would join RISC-V International as a premier member. Intel Foundry Services (IFS) will embrace designs built on multiple ISAs in order to compete with foundry giants Taiwan Semiconductor Manufacturing Co. and Samsung. Intel claims to be the only foundry offering IP optimized for x86, Arm and RISC-V.
The wording is crucial here, acknowledging as it does that RISC-V is joining x86 and Arm as a leading chip architecture.
Tomi Engdahl says:
Currently on GroupGets, CLEAR is a fully open source ASIC with an embedded FPGA and RISC-V core.
Efabless’ CLEAR Is a Fully Open Source ASIC with Embedded FPGA and RISC-V Core, Now on GroupGets
https://www.hackster.io/news/efabless-clear-is-a-fully-open-source-asic-with-embedded-fpga-and-risc-v-core-now-on-groupgets-8ed72c5cff6a
Designed to introduce people to the chipIgnite custom ASIC production platform, CLEAR is at once a functional dev board and a tech demo.
Chip design specialist Efabless has launched an open source FPGA chip dubbed CLEAR, built on its own chipIgnite platform and offering a completely open design — right down to its CPU core.
“CLEAR is an open source FPGA ASIC delivered to you on its development board and its open source software development tools and all the ASIC [Application Specific Integrated Circuit] design tools used to create it,” Efabless explains of the project. “That’s for you to create your own – yes that’s right – ASIC.”
Tomi Engdahl says:
Renesas laajensi 64-bittisiin RISC-V-ohjaimiin
https://etn.fi/index.php/13-news/13242-renesas-laajensi-64-bittisiin-risc-v-ohjaimiin
Japanilainen Renesas Electronics on julkistanut 64-bittiseen RISC-V-ytimeen perustuvien ohjainpiirien sarjan. RZ/Five-perhe käyttää Andes Technologyn AX45MP-ytimeen. RISC-V:n asema vahvistuu näin Renesasin Arm-pohjaisten ohjaimien rinnalla.
RZ/Five on markkinoiden ensimmäinen yleiskäyttöinen mikroprosessori, joka on rakennettu Andesin 64-bittisen RISC-V-ytimen ympärille. Aiemmin Andes on tehnyt yhteistyötä Renesasin kanssa ensin 32-bittisessä RISC-V-ytimessä. Renesasin mukaan RISC-V sopii ihanteellisesti IoT-päätelaitteisiin.
Tomi Engdahl says:
RZ/Five (RISC-V)
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
https://www.renesas.com/eu/en/document/mah/fzfive-rzg-series-2nd-generation-overview-users-manual-hardware?language=en&r=1569466
Tomi Engdahl says:
https://www.uusiteknologia.fi/2021/12/23/uuden-ajan-supersuorittimet-armv9-ja-muu-kisaajat/
Tomi Engdahl says:
Renesas Pioneers RISC-V Technology With RZ/Five General-Purpose MPUs Based on 64-Bit RISC-V CPU Core
Expands the RZ Family Portfolio by Adding to Existing Arm CPU Core–Based MPUs
https://www.renesas.com/eu/en/about/press-room/renesas-pioneers-risc-v-technology-rzfive-general-purpose-mpus-based-64-bit-risc-v-cpu-core
Tomi Engdahl says:
Renesas introduces RZ/Five Linux-capable 64-bit RISC-V microprocessor family
https://www.cnx-software.com/2022/03/04/renesas-introduces-rz-five-linux-capable-64-bit-risc-v-microprocessor-family/
Renesas has launched its first RISC-V processor family with the RZ/Five general-purpose microprocessors based on an Andes AX45MP 64-Bit RISC-V CPU core, and with long-term Linux support via the industrial-grade CIP Linux that offers maintenance for over 10 years.
The RISC-V processor is pin-to-pin compatible with the Arm Cortex-A55/M33–based RZ/G2UL processor family, and while being a general-purpose family, the RZ/Five chips are specifically well-suited to IoT endpoint devices such as gateways for solar inverters or home security systems.
Tomi Engdahl says:
RISC-V AI Chips Will Be Everywhere Esperanto Techology’s chip heralds new era in open-source architecture; Intel set to cash in
https://spectrum.ieee.org/risc-v-ai?share_id=6925155
Tomi Engdahl says:
RISC-V AI Chips Will Be Everywhere Esperanto Techology’s chip heralds new era in open-source architecture; Intel set to cash in
https://spectrum.ieee.org/risc-v-ai
Tomi Engdahl says:
Codasip Launches New L11, L31 RISC-V Cores with TinyML TensorFlow Lite for Microcontrollers Support
Edge AI focus for the company’s latest embedded cores brings with it the promise of TensorFlow Lite support across its whole range.
https://www.hackster.io/news/codasip-launches-new-l11-l31-risc-v-cores-with-tinyml-tensorflow-lite-for-microcontrollers-support-70efbff38258
Tomi Engdahl says:
ARM:n kisaaja vahvistuu uutuuspiireillä
https://www.uusiteknologia.fi/2022/03/07/armn-kisaaja-vahvistuu-uutuuspiireilla/
Berkeleyn yliopistossa kehitetty avoin RISC-V-prosessoriarkkitehtuuri on saanut koko ajan uusia tukijoita. Erityisesti RISC-V on kerännyt suosiota sulautetuissa ohjainpiirityyppisissä sovelluksissa juuri muunneltavuutensa ansiosta. Uusimpana mukaan on lähtenyt Renesas uudella RZ/Five-piirisarjallaan.
Uusimpana RISC-V-junaan on hypännyt japanilainen Renesas, joka on tuomassa tarjolle RISC-V-pohjalle rakennetut RZ/Five-sarjan mikroprosessoriyksiköt (MPU). Ne on rakennettu Risc-V:n 64-bittisen CPU -version ympärille.
RZ/Five (RISC-V)
General-purpose Microprocessors with RISC-V CPU Core (Andes AX45MP Single) (1.0 GHz) with 2ch Gigabit Ethernet
https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet
Tomi Engdahl says:
https://hackaday.com/2022/03/06/hackaday-links-march-6-2022/
If you’re into embedded design and RT-Thread, you might want to take a look at the contest LCSC and other companies are sponsoring. The challenge is to come up with a design that uses the CH32V307, a 32-bit RISC-V microcontroller. Whatever you come up with needs to use RT-Thread as an OS. If you’ve got an embedded idea that you’re itching to try, this might be a good contest to try. Accepted entries all get either a CH32V307 dev board or chip, and you have until April 30 to get your entry in.
Hack it! RISC-V Design Challenge
With RISC-V becoming more and more popular, in order to let developers further understand the application and hands-on development of RISC-V MCU, WCH, RT-Thread, LCSC, and EasyEDA jointly hold this international and national RISC-V design challenge.
https://www.lcsc.com/faqs?id=85
Tomi Engdahl says:
Työkalut ilmaiseksi RISC-V-kehitykseen
https://etn.fi/index.php/13-news/13290-tyoekalut-ilmaiseksi-risc-v-kehitykseen
Saksalainen sulautettujen sovellusten työkaluja kehittävä SEGGER on ilmoittanut yhteistyöstään mikro-ohjainvalmistaja HPMicro Semiconductorin kanssa. Mikäli asiakas ostaa HPMicron RISC-V-pohjaisen HPM6000-sarjan ohjainpiirin, saa SEGGERin IDE Embedded Studion maksutta käyttöönsä.
Embedded Studio sisältää kaikki työkalut ja ominaisuudet, joita odotetaan virtaviivaistettuun, ammattimaiseen sulautettuun C- ja C++-kehitykseen.
HPMicron reaaliaikainen RISC-V-mikro-ohjainsarja HPM6000 julkaistiin joulukuussa 2021 ja on täydessä tuotannossa. Yhtiön mukaan sarjan lippulaivapiiri HPM6750 on saavuttanut uudet suorituskykyennätykset – yli 9000 CoreMark-pistettä ja 4500 DMIPS:ä – kahdella RISC-V-ytimellä, jotka toimivat jopa 800 megahertsin taajuudella.
https://www.segger.com/products/development-tools/embedded-studio
Tomi Engdahl says:
Kit Close-Up: Lattice Semiconductor’s Crosslink-NX Development Kit
Nov. 13, 2021
Editor Bill Wong examines this FPGA development platform, which supports soft core processors like RISC-V.
https://www.electronicdesign.com/technologies/embedded-revolution/video/21177784/electronic-design-kit-closeup-lattice-semiconductors-crosslink-nx-development-kit
Tomi Engdahl says:
https://etn.fi/index.php/13-news/13297-iar-laajensi-risc-v-tuen-64-bittisiin
Tomi Engdahl says:
Adafruit Industries has confirmed that its QT Py ESP32-C3, the company’s first development board built around the free and open source RISC-V instruction set architecture, is coming soon — and at under $10.
Adafruit’s QT Py ESP32-C3, Its First RISC-V Dev Board, Begins Rolling Off the Production Line
https://www.hackster.io/news/adafruit-s-qt-py-esp32-c3-its-first-risc-v-dev-board-begins-rolling-off-the-production-line-3cf4af2afb1d
Tiny board with a 160MHz RISC-V core, 400kB of SRAM, 4MB flash, Wi-Fi, and BLE 5.0 to hit the Adafruit store soon.
Adafruit has confirmed that its QT Py ESP32-C3, the company’s first development board built around the free and open source RISC-V instruction set architecture, is coming soon — and at under $10.
“This is going to be our first RISC-V based dev board,” explains Adafruit’s Phillip Torrone of the latest entry in the diminutive QT Py family of boards, “and isn’t that something to celebrate? It’s a QT Py based on the ESP32-C3 which is a Wi-Fi + BLE chipset with RISC-V instead of [the] Tensilica core.”
Espressif announced the ESP32-C3 at the tail end of 2020 as a drop-in pin-compatible replacement for the popular ESP8266 microcontroller. At its heart is a 32-bit single-core microcontroller, built atop the free and open-source RISC-V instruction set architecture, running at up to 160MHz alongside 400kB of static RAM (SRAM) and radios for 2.4GHz Wi-Fi and Bluetooth Low Energy (BLE) 5.0.
Tomi Engdahl says:
Clockwork Pi Launches “Highly Experimental” RISC-V Variant of Its Compact DevTerm Portable PC
Powered by the Allwinner D1 and 1GB of DDR3 memory, the new DevTerm variant aims at enthusiast experimenters rather than beginners.
https://www.hackster.io/news/clockwork-pi-launches-highly-experimental-risc-v-variant-of-its-compact-devterm-portable-pc-021ad546e675
Tomi Engdahl says:
Intel SVP in China: Chinese Chipmakers Could Become Strong Rivals by 2025 (Updated)
By Mark Tyson published 1 day ago
No specific CPU firms were highlighted
https://www.tomshardware.com/news/chinese-cpus-could-catch-up-by-2025
Tomi Engdahl says:
Developing Automotive Software
March 1, 2022
Green Hills Software was showing off automotive tools and frameworks including support for ROS 2 and RISC-V at CES 2022.
https://www.electronicdesign.com/markets/automotive/video/21234361/electronic-design-developing-automotive-software?utm_source=EG%20ED%20Auto%20Electronics&utm_medium=email&utm_campaign=CPS220314013&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
Tomi Engdahl says:
https://www.tomshardware.com/news/devterm-embraces-riscv
Tomi Engdahl says:
SiFive Raises $175 Million to Take Fight to Arm with RISC-V
March 17, 2022
To date, the company has raised more than $350 million in funding to build out its core chip design business.
https://www.electronicdesign.com/technologies/embedded-revolution/article/21236237/electronic-design-sifive-raises-175-million-to-take-fight-to-arm-with-riscv
Tomi Engdahl says:
The Tiny iCESugar-nano Packs an FPGA, RISC-V Core, and iCELink Into a Compact Footprint
A low-cost design with an open source toolchain, the iCESugar-nano punches well above its diminutive weight.
https://www.hackster.io/news/the-tiny-icesugar-nano-packs-an-fpga-risc-v-core-and-icelink-into-a-compact-footprint-1cf822117d44
Tomi Engdahl says:
https://www.edn.com/gpu-specialist-imagination-to-create-250-engineering-jobs-in-2022/?utm_source=edn_facebook&utm_medium=social&utm_campaign=Articles
It’s mainly the demand in the IP industry that has filled Imagination’s office in Cambridge. The company continues to build its IP portfolio with more than 2,800 patents and applications. For instance, last year, Imagination unveiled Catapult, its first CPU based on RISC-V, as well as IMG CXT, an advanced ray-tracing GPU.
Tomi Engdahl says:
AMD Job Posting Hints at Embedded RISC-V CPUs
By Anton Shilov published 1 day ago
There is a RISC-V CPU development team at AMD.
https://www.tomshardware.com/news/amd-developing-embedded-64-bit-risc-v-cpu
Tomi Engdahl says:
Linux 5.17 release – Main changes, Arm, RISC-V, and MIPS architectures
https://www.cnx-software.com/2022/03/21/linux-5-17-release-main-changes-arm-risc-v-and-mips-architectures/
Tomi Engdahl says:
Chip Designer SiFive Raises $175M To Take On Heavyweight Arm Ltd
https://thetechee.com/chip-designer-sifive-raises-175m-to-take-on-heavyweight-arm-ltd/
SiFive, a chip design startup based in California, has raised considerable funds to take on heavyweights in the industry, mainly Arm Ltd, the British chip design giant. The startup recently raised $175mn in fresh funding at a $2.5bn valuation. Coatue Management, a blue-chip tech-focused investment firm, led the round.
SiFive designs computing chips based on the open-source RISC-V architecture and license its designs to hardware producers. The company was founded by the inventors of RISC-V at the University of California, Berkeley, in 2015.
Tomi Engdahl says:
https://hackaday.com/2022/03/19/clockwork-devterm-r-01-takes-risc-v-out-for-a-spin/
Tomi Engdahl says:
RISC-V tuo tekoälyn reunalaitteisiin
https://etn.fi/index.php?option=com_content&view=article&id=13329&via=n&datum=2022-03-21_15:51:44&mottagare=30929
Yhä useammin tekoälyä halutaan hyödyntää verkon reunalla. Näin dataa ei tarvitse siirtää pilveen, mikä parantaa tietoturvaa. Saksalaisen Fraunhofer-insituutin optiikan mikroelektronisia järjestelmiä kehittävä yksikkö IPMS on kehittänyt RISC-V-pohjaisen ytimen, jolla tekoälyprosessointi tuodaan verkon reunalle.
Fraunhofer Institute for Photonic Microsystems tarjoaa valmiita, alustasta riippumattomia IP-ydinmoduuleja. IP-moduulien avulla kehittäjät voivat toteuttaa erilaisia piiriratkaisuja: SoC-järjestelmäpiirejä, mikro-ohjaimia, FPGA-piirejä ja ASICeja. Tämä mahdollistaa kehitysaikojen ja -kustannusten huomattavan pienentämisen.
Uusi RISC-V-käskysarjaan perustuva EMSA5 pitää sisällään Tensorflow Lite -tuen. Sen avulla voidaan päätellä esimerkiksi anturidatasta poikkeavuuksia suoraan verkon reunalla. Toinen käyttötapa AI-algoritmeille on eleohjauksen tulkinta.
Tomi Engdahl says:
Linux 5.17 release – Main changes, Arm, RISC-V, and MIPS architectures – CNX Software
https://www.cnx-software.com/2022/03/21/linux-5-17-release-main-changes-arm-risc-v-and-mips-architectures/
Tomi Engdahl says:
Now The V In RISC-V Stands For VRoom
https://hackaday.com/2022/03/26/now-the-v-in-risc-v-stands-for-vroom/
Hundreds of variations of open-source CPUs written in an HDL seem to float around the internet these days (and that’s a great thing). Many are RISC-V, an open-source instruction set (ISA), and are small toy processors useful for learning and small tasks. However, if you’re [Paul Campbell], you go for a high-end super-scalar, out-of-order, speculative, 8 IPC monster of a RISC-V CPU known as VRoom!.
That might seem a bit like word soup to the uninitiated in the processor design world (which is admittedly relatively small) but what makes this different from VexRISC is the scale and complexity. Rather than executing one instruction at a time sequentially, it executes multiple instructions, completing them concurrently in whatever order it can handle. The VexRISC chip is a good 32-bit modular design that can run Linux. It pulls a solid 1.57 DMIPS/MHz with everything turned on. The VRoom already clocks in at mighty 6.5 DMIPS/MHz, with more performance gains. It peaks at 8 instructions every clock cycle with a dual register file and a clever committing system to keep up.
https://moonbaseotago.github.io/
Tomi Engdahl says:
Dongshan Nezha STU devkit features Allwinner D1 RISC-V SoM/SBC
content://com.android.chrome.FileProvider/offline-cache/19624e7a-261c-465b-8835-ce6d633f1e30.mhtml
Tomi Engdahl says:
Developing Automotive Software
March 1, 2022
Green Hills Software was showing off automotive tools and frameworks including support for ROS 2 and RISC-V at CES 2022.
https://www.electronicdesign.com/markets/automotive/video/21234361/electronic-design-developing-automotive-software?utm_source=EG+ED+Auto+Electronics&utm_medium=email&utm_campaign=CPS220314013&o_eid=7211D2691390C9R&rdx.ident%5Bpull%5D=omeda%7C7211D2691390C9R&oly_enc_id=7211D2691390C9R
The electric BMW iX was on display and Green Hillls tools and software were part of the mix. The discussion also touched on Green Hills’ support for the eSync Alliance that just announced their eSync 2.0 specification for over-the-air (OTA) udpates.
Robert also talked about the company’s collaboration with Apex.AI and their Robot Operating System, ROS 2-based ApexOS and middleware. This combination looks to streamline the safe and secure development of automotive software for advanced driver-assistance systems (ADAS) and self-driving cars that meet standards like ISO 26262.
https://www.ros.org/
Tomi Engdahl says:
RISC-V-moniydinprosessoreja helpommin piille
https://etn.fi/index.php/13-news/13417-risc-v-moniydinprosessoreja-helpommin-piille
Avoin RISC-V-arkkitehtuuri kasvattaa nyt nopeasti suosiotaan. Yksi alueen pioneereista on ytimiä kehittävä Andes Technology. Sen uusittu työkalupaketti helpottaa moniydinpohjaisten suunnittelujen tuomista markkinoille.
AndeSight IDE v5.1 tuo sovelluskehityksen, virheenkorjauksen ja analyysin tehon heterogeenisiin RISC-V-moniprosessoreihin. Työkalut tukevat esimerkiksi Andesin uutta superskalaarisa moniydinprosessoria A(X)45MP:tä ja Andesin vektoriprosessori NX27V:tä.
Tomi Engdahl says:
https://etn.fi/index.php/13-news/13417-risc-v-moniydinprosessoreja-helpommin-piille
Avoin RISC-V-arkkitehtuuri kasvattaa nyt nopeasti suosiotaan. Yksi alueen pioneereista on ytimiä kehittävä Andes Technology. Sen uusittu työkalupaketti helpottaa moniydinpohjaisten suunnittelujen tuomista markkinoille.
AndeSight IDE v5.1 tuo sovelluskehityksen, virheenkorjauksen ja analyysin tehon heterogeenisiin RISC-V-moniprosessoreihin. Työkalut tukevat esimerkiksi Andesin uutta superskalaarisa moniydinprosessoria A(X)45MP:tä ja Andesin vektoriprosessori NX27V:tä.
Työkalut tuovat symmetrisen multiprosessoinnin eli SMP-tuen suunnitteluun aiemman Linux SMP:n lisäksi Ensimmäistä kertaa Andes on portannut Zephyr RTOS:n RISC-V-arkkitehtuuriin. Tuki kattaa Zephyrin ohjainalijärjestelmän.
Tomi Engdahl says:
BrainChip, SiFive Announce Partnership for High-Performance, Low-Power On-Device Edge AI
https://www.hackster.io/news/brainchip-sifive-announce-partnership-for-high-performance-low-power-on-device-edge-ai-647a96c595a6
Spiking neural network acceleration on one side and high-performance low-power RISC-V on the other could make for an edge AI match-up.
Tomi Engdahl says:
MangoPi MQ Pro – A $20 RISC-V alternative to Raspberry Pi Zero W
https://www.cnx-software.com/2022/04/09/mangopi-mq-pro-a-20-risc-v-alternative-to-raspberry-pi-zero-w/
MangoPi MQ Pro is an Allwinner D1 RISC-V SBC that offers an alternative to Raspberry Pi Zero W with the same form factor, and most of the same features including WiFi and Bluetooth connectivity
Tomi Engdahl says:
RISC-V takes steps to minimize fragmentation
Steering body calls for help to ‘identify ISA gaps, build plans for future extensions’
https://www.theregister.com/2022/04/01/riscv_fragmentation/
Tomi Engdahl says:
The Bee Motion Mini Is a RISC-V-Powered Arduino-Compatible Miniature Motion-Detecting Marvel
https://www.hackster.io/news/the-bee-motion-mini-is-a-risc-v-powered-arduino-compatible-miniature-motion-detecting-marvel-98db2506ddf8
Designed for remote deployment, this compact sensor board can connect over Bluetooth 5.0 Low Energy (BLE), Bluetooth Mesh, or Wi-Fi.
Tomi Engdahl says:
https://www.theregister.com/2022/04/22/samsung_esperanto_riscv/