Can RISC-V – Linux of Microprocessors – Start an Open Hardware Renaissance?

https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance

RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market? 

18 Comments

  1. Tomi Engdahl says:

    Over the past few months, we’ve seen a few new microcontrollers built around the RISC-V core. The first is the HiFive1, a RISC-V on an Arduino-shaped board. The Open-V is another RISC-V based microcontroller, and now it too supports the Arduino IDE. That may not seem like much, but trust me: setting up the HiFive1 toolchain takes at least half an hour.

    Source: http://hackaday.com/2017/01/22/hackaday-links-january-22-2017/

    Reply
  2. Tomi Engdahl says:

    risk-vee
    An as-small-as-possible RISC-V implementation in Logisim.
    https://hackaday.io/project/18859-risk-vee

    Reply
  3. Tomi Engdahl says:

    System Bits: April 18
    http://semiengineering.com/system-bits-april-18/

    Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips.

    In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that, if uncorrected, the problems could cause errors in software running on RISC-V chips. According to the researchers, officials at the RISC-V Foundation said the errors would not affect most versions of RISC-V but would have caused problems for higher-performance systems.

    “Incorrect memory access orderings can result in software performing calculations using the wrong values. These in turn can lead to hard-to-debug software errors that either cause the software to crash or to be vulnerable to security exploits. With RISC-V processors often envisioned as control processors for real-world physical devices (i.e., internet of things devices) these errors can cause unreliability or security vulnerabilities affecting the overall safety of the systems.”

    “RISC-V is in the fortunate position of being able to look back on decades’ worth of industry and academic experience,” he said. “It will be able to learn from all of the insights and mistakes made by previous attempts.”
    The RISC-V project essentially offers specifications that guide the hardware and software design of RISC-V processors and software applications.

    Martonosi’s team discovered the problems when testing their new system to check memory operations across any computer architecture. The system, called TriCheck, allows designers and others interested in working with a design, to detect memory ordering errors before they become a problem.

    Tool checks computer architectures, reveals flaws in emerging design
    http://www.princeton.edu/engineering/news/archive/?id=17707

    The researchers, testing a technique they created for analyzing computer memory use, found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture. The researchers warned that, if uncorrected, the problems could cause errors in software running on RISC-V chips. Officials at the RISC-V Foundation said the errors would not affect most versions of RISC-V but would have caused problems for higher-performance systems.

    Krste Asanović the chair of the RISC-V Foundation, welcomed the researchers’ contributions. He said the RISC-V Foundation has formed a working group, headed by Martonosi’s former graduate student and co-researcher Daniel Lustig, to solve the memory-ordering problems. Asanović, a professor of electrical engineering and computer science at the University of California-Berkeley, said the RISC-V project was looking for input from the design community to “fill the gaps and the holes and getting a spec that everyone can agree on.”

    “The goal is to ratify the spec in 2017,” he said. “The memory model is part of that.”

    “We call it TriCheck because it is making sure that the memory-ordering guarantees made by these three levels are in alignment,” Martonosi said.

    In a paper presented April 10 at the ACM International Conference on Architectural Support for Programming Languages and Operating Systems, the researchers describe the TriCheck system.

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  4. Tomi Engdahl says:

    RISC-V Cores Get Support, Fees
    Silicon IP offered as try-and-buy online
    http://www.eetimes.com/document.asp?doc_id=1331690&

    Instruction sets may want to be free, but cores–maybe not so much. Startup SiFive announced a new embedded RISC-V core and a relatively simple way to access its processor cores on its Web site, however, they come with one-time licensing costs in the mid-six figures.

    SiFive made its existing 32-bit E31 core and a new 64-bit E51 version available for one-time fees of about $300,000 and $600,000, respectively. An open source core called Rocket created by some of SiFive’s founders remains available for free online. It can be used to configure and generate 32- and 64-bit processor cores.

    The SiFive news comes just before the sixth workshop of the RISC-V open instruction set group, its first in China.

    SiFive will have to compete with a wide range of cores from Cadence, Cortus, Imagination, Synopsys and Andes–which rolls out its first 64-but core next week. The existing players have more mature ecosystems and cores that also sell for less than a million dollars, said Linley Gwennap, principal of the Linley Group (Mountain View, Calif.).

    “A year ago there was quite a debate if people would license a core if there was a free version, [but now] we’ve seen significant demand for customers who don’t want an open-source version but one better documented with a company behind it,” said Jack Kang, vice president of product and business development at SiFive.

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  5. Tomi Engdahl says:

    Agam Shah / PCWorld:
    SiFive, creators of open RISC-V architecture, announce $8.5M Series B led by Spark Capital as company unveils two new chip designs

    Open-source chip mimics Linux’s path to take on closed x86 and ARM CPUs
    The RISC-V chip design can be licensed from SiFive
    http://www.pcworld.com/article/3194357/internet-of-things/open-source-chip-mimics-linuxs-path-to-take-on-closed-x86-arm-cpus.html

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  6. Tomi Engdahl says:

    Andes, First Mainstream CPU IP Provider to Adopt RISC-V, Expands Product Line with New 64bit Processor IP
    http://www.digitaljournal.com/pr/3337445

    Andes Technology Corporation, the leading Asia-based supplier of high performance, low-power, small embedded CPU cores serving 2-billion SoCs, today announced a new generation of the AndeStar™ architecture. In the process, Andes becomes the first mainstream CPU IP provider to adopt RISC-V, the open RISC Instruction Set Architecture (ISA) developed at the University of California Berkeley. Andes ISA, called AndeStar™ V5, supports 64-bits and the widely known RISC-V ISA as its subset and will bring the open, compact, and modular RISC-V into mainstream SoC applications.

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  7. Tomi Engdahl says:

    Wednesday 11 00am Keynote Address Impedance Matching Expectations Between RISC V and the Open Hardware
    https://www.youtube.com/watch?v=zXwy65d_tu8

    Reply
  8. Tomi Engdahl says:

    Memory Model Verification at the Trisection of Software, Hardware, and ISA (Princeton)
    https://semiengineering.com/memory-model-verification-at-the-trisection-of-software-hardware-and-isa-princeton/

    Princeton University researchers have discovered a series of errors in the RISC-V instruction specification

    Princeton University researchers have discovered a series of errors in the RISC-V instruction specification that now are leading to changes in the new system, which seeks to facilitate open-source design for computer chips. In testing a technique they created for analyzing computer memory use, the team found over 100 errors involving incorrect orderings in the storage and retrieval of information from memory in variations of the RISC-V processor architecture.

    TriCheck: Memory Model Verification at the
    Trisection of Software, Hardware, and ISA
    http://mrmgroup.cs.princeton.edu/papers/ctrippel_ASPLOS17.pdf

    Reply
  9. Tomi Engdahl says:

    VexRiscv: A Modular RISC-V Implementation for FPGA
    http://hackaday.com/2017/07/21/vexriscv-a-modular-risc-v-implementation-for-fpga/

    Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.

    SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.

    When you build a CPU in FPGA, you generally have to make one of three choices. You can roll your own, which is great fun but requires a lot of work both on the design and the associated tools, for example, a cross-compiler or operating system. You can “borrow” an existing architecture or design which may or may not be legal, depending on what you pick. You can also use a commercial offering. While some of these are free in some circumstances, you’ll pay for anything substantial.

    This open implementation offers you an easy way to leverage some great tools. There’s a debugging interface for GDB and a FreeRTOS port. You have a 32-bit part that can achieve 1.16 Dhrystone MIPS/MHz even with all features turned on. This is comparable to commercial 32-bit processors.

    A FPGA friendly 32 bit RISC-V CPU implementation
    https://github.com/SpinalHDL/VexRiscv

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  10. Tomi Engdahl says:

    RISC-V and The Birth of the New Computer Architecture Ecosystem
    https://www.mentor.com/embedded-software/blog/post/risc-v-and-the-birth-of-the-new-computer-architecture-ecosystem-0e4acb6b-4f9f-4b2e-91a9-884d5e3f4e56?contactid=1&PC=L&c=2017_07_27_esd_newsletter_update_v7_july

    It is not often you get to watch the birth of a new computer architecture ecosystem unfold. Announced in 2010, RISC-V has recently seen an increase in momentum as measured in the public development activity of software required to make RISC-V useful. This may seem like an odd way to measure momentum (sorry physicists!), but these are necessary steps for wider adoption of the new open instruction set architecture. As these tools mature they will form the basis for enabling more exotic variants and implementations of the RISC-V architecture. Note that there is already shipping RISC-V hardware in the form of a development kit from SiFive.

    Hardware Enablement: Software Makes Hardware Useful

    New hardware doesn’t do anything without software. The shortest path to making a new architecture useful is not to write new assemblers, compilers and related software tools but instead extend existing software tools like binutils and gcc so that they support the new architecture. Extending these tools to support a new architecture is called adding a backend port.

    To add new hardware support to an existing toolchain or operating system simply pick a recent snapshot of the codebase, make a local development copy, make the required changes, and release a toolchain and OS. If you would like to follow along with the early RISC-V software you can see the work in progress here in the RISC-V git repos.

    https://github.com/riscv/

    Reply
  11. Tomi Engdahl says:

    RISC-V Pros And Cons
    https://semiengineering.com/risc-v-pros-cons/

    Proponents tout freedom for computing architectures, but is the semiconductor ecosystem ready for open-source hardware?

    Simpler, faster, lower-power hardware with a free, open, simple instruction set architecture? While it sounds too good to be true, efforts are underway to do just that with RISC-V, the instruction-set architecture (ISA) developed by UC Berkeley engineers and now administered by a foundation.

    “The money shouldn’t be going into the processors, necessarily,” said Ted Speers, senior technical director, product architecture and planning for Microsemi‘s SoC business unit, and board member of RISC-V Foundation. “The processor cost should come down, and then you innovate on top of that with accelerators, new architectures, and so forth.”

    Technically, the ability to manage complexities has expanded to the point where a 32-bit RISC microprocessor is not considered a complex object anymore, noted Drew Wingard, CTO of Sonics.

    “The barrier to entry as a microprocessor instruction set architecture is all about the software and the ecosystem,” he said. “There’s no magic in the underlying technology for microprocessors, in general. RISC-V essentially takes that to the next logical level to say, ‘Let’s try to capture an instruction set architecture together with enough structure and automation that allows us to build families of processors much more easily. And, we’ll choose to distribute it as an open source piece of IP so that the community can add on.’ It has aspects of the open source movement, it has aspects of the configurable processor movement, and it has the opportunity to restructure how we think about the costs of microprocessor IP.”

    The business end of this market will likely the same model as Linux, where commercial vendors add in their own IP and support. Commercial suppliers of RISC-V cores include Nvidia, Andes Technology, Cortus, and Codasip.

    The main ISAs used today are x86, ARM, ARC, MIPS and PowerPC, along with other ISAs used under the hood in GPUs and DSPs. But RISC-V is starting to make some inroads. Nvidia announced that its SoCs will contain a RISC-V control processor. Andes Technology, a softcore supplier, likewise adopted RISC-V in its 64-bit architecture.

    RISC-V from an architecture standpoint, is both simple and elegant

    “The key question is software ecosystems,” Mohandass said. “How are they going to develop? It’s the whole chicken-and-egg problem.”

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  12. Tomi Engdahl says:

    Rambus Adds Security to RISC-V
    Block is first in new SiFive IP program
    http://www.eetimes.com/document.asp?doc_id=1332175&

    Startup SiFive announced a new program providing third-party intellectual property blocks for its RISC-V processors. Its first partnership is for security hardware from Rambus.

    Rambus will provide a crypto core optimized to connect to its IoT device management services and run on the SiFive Freedom chips. The Rambus core enables a secure connection, attestation and device monitoring, said Martin Scott, general manager of Rambus’s security group.

    The core is the first member of what SiFive calls DesignShare. “SiFive welcomes everybody to join DesignShare — Rambus is the first of many partners we will be announcing soon,” said Jack Kang, vice president of product and business development at the startup.

    The program aims to deliver IP “at a low or reduced up front cost,” he said. The blocks will not necessarily be based on open source code.

    SiFive officially launched in May its first two cores available on its Web site. Although the RISC-V instruction set is open source, the cores require a one-time licensing fee. SiFive does not charge per-unit royalties.

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  13. Tomi Engdahl says:

    The open processor got its own ecosystem

    RISC-V is an open-source processor based on the popular ARM architecture. Microsemi now says it has set up a Mi-V ecosystem to promote the introduction of an open processor.

    RISC-V is a command line for embedded processors managed by the RISC-V Foundation. Its advantages are explicitly based on the open source code, allowing cores to be developed faster than in a closed ecosystem such as ARM.

    The Mi-V ecosystem has included, for example, RTOS embedded embedded Micrium and Express Logic, whose Thread OS is one of the most popular embedded device RTOSs.

    Microsemi is one of the pioneers of the RISC-V project.

    Source: http://etn.fi/index.php?option=com_content&view=article&id=7035&via=n&datum=2017-10-20_15:46:48&mottagare=31202

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  14. Tomi Engdahl says:

    RISC-V Spins into Drives, AI
    Western Digital, Esperanto tip plans for chips
    https://www.eetimes.com/document.asp?doc_id=1332658&_mc=RSS_EET_EDT

    Storage giant Western Digital announced that it will standardize on RISC-V processors and has invested in Esperanto Technologies, a startup designing high-end SoCs and cores using the open-source instruction set architecture. The two moves suggest that RISC-V has emerged as a viable — but not yet mature — alternative to ARM and the x86.

    Long-term, WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. Privately, the company also revealed that it is working on machine-learning accelerators for inference, probably related to its unspecified investment in Esperanto.

    For its part, the startup tipped plans for a family of 64-bit RISC-V chips that will include:

    An AI “supercomputer-on-a-chip” to be made in TSMC’s 7-nm process.
    A 16-core “ET-Maxion” targeting highest single-thread performance
    A 4,096-core “ET-Minion” targeting performance-per-watt with a vector floating-point unit in each core.

    “Having a major company like WD bet on the architecture is a huge boost for the RISC-V ecosystem, and having a startup try to take it to high-end products is a big deal because to date, RISC-V has been mainly in low-end microcontrollers for the IoT,” said Linley Gwennap, principal of market watcher The Linley Group.

    At a RISC-V workshop here, Esperanto will demonstrate RTL, presumably running in an FPGA, handling neural-networking jobs such as image recognition. The company’s general-purpose processors haven’t taped out yet but will target a range of applications.

    “Top of our apps list is training and inference; we can do pretty good at graphics for high-end VR/AR … [the architecture] works best for problems with lots of parallelism,” said Ditzel.

    Unlike training accelerators from rivals such as Nvidia, Intel, and startup Graphcore, “we’re not at a max reticle die size,” he said of the 7-nm chip.

    The startup’s main business will be selling SoCs; however, it also may sell systems using them. In addition, it is open to licensing its cores “to make RISC-V more widespread.”

    The relative immaturity of RISC-V and software for it is a chief challenge today.

    “The GCC compiler is pretty stable and Linux ports are being upstreamed, but LLVM still has ways to go,” said Ditzel. “By the time we are selling chips, there will be a lot more maturity. There hasn’t been much silicon until recently with the SiFive parts, but once that’s there, the software will come along.”

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  15. Tomi Engdahl says:

    RISC-V Spins into Drives, AI
    Western Digital, Esperanto tip plans for chips
    https://www.eetimes.com/document.asp?doc_id=1332658

    Long-term, WD expects that it could ship as many as 2 billion RISC-V chips a year inside its hard-disk and solid-state drives. Privately, the company also revealed that it is working on machine-learning accelerators for inference, probably related to its unspecified investment in Esperanto.

    For its part, the startup tipped plans for a family of 64-bit RISC-V chips that will include:

    An AI “supercomputer-on-a-chip” to be made in TSMC’s 7-nm process.
    A 16-core “ET-Maxion” targeting highest single-thread performance
    A 4,096-core “ET-Minion” targeting performance-per-watt with a vector floating-point unit in each core.

    “Having a major company like WD bet on the architecture is a huge boost for the RISC-V ecosystem,

    Reply
  16. Tomi Engdahl says:

    RISC-V Processor Developer Suite Announced by Imperas
    http://www.imperas.com/articles/risc-v-processor-developer-suite-announced-by-imperas

    Oxford, United Kingdom, November 29th, 2017 – Imperas Software Ltd., the leader in high-performance software simulation and virtual platforms, today announced the release of its new RISC-V Processor Developer Suite™. The RISC-V Processor Developer Suite contains the models and tools necessary to validate and verify the functionality of a RISC-V processor. It also enables the early estimation of timing performance and power consumption for the processor.

    The Imperas RISC-V Processor Developer Suite delivers commercially supported models, the fastest software simulator and a suite of tools:

    Infrastructure to easily evaluate RISC-V conformance
    Reference models for design verification
    Standard software tool chains including compiler, linker, debugger, and Eclipse integration
    Fast Processor Models, Instruction Set Simulator (ISS) and extendable virtual platforms
    Processor model instruction code coverage and profiling
    Timing performance and power estimation tools
    Many test suites, with different goals, to measure and maintain processor quality

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  17. Tomi Engdahl says:

    Western Digital Transitions to RISC-V Open-Source Architecture for Big Data, IoT
    https://www.designnews.com/electronics-test/western-digital-transitions-risc-v-open-source-architecture-big-data-iot/96736693957917?ADTRK=UBM&elq_mid=2300&elq_cid=876648

    Western Digital believes open-source architecture is the best solution for Big Data and Fast Data and has committed to transition all of its cores to RISC-V.

    Reply

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