Can RISC-V – Linux of Microprocessors – Start an Open Hardware Renaissance?

https://www.darrentoback.com/can-risc-v-linux-of-microprocessors-start-an-open-hardware-renaissance

RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market? 

646 Comments

  1. Tomi Engdahl says:

    Pine64 Unveil Star64 RISC-V Raspberry Pi Alternative
    By Ian Evenden published about 21 hours ago
    A ‘Stellar’ Raspberry Pi Alternative
    https://www.tomshardware.com/news/pine64-star64-revealed

    Reply
  2. Tomi Engdahl says:

    PINE64 Formally Unveils the StarFive JH7110-Powered Star64 RISC-V Single-Board Computer
    With four processor cores, 8GB of RAM, dual gigabit Ethernet, PCIe, and a graphics processor, this StarFive JH7110-based board impresses.
    https://www.hackster.io/news/pine64-formally-unveils-the-starfive-jh7110-powered-star64-risc-v-single-board-computer-3917fae60eb9

    Reply
  3. Tomi Engdahl says:

    Dual-Core RISC-V Linux at Your Fingertips: Hands-On with the StarFive VisionFive V1 8GB SBC
    Built around the JH7100 system-on-chip, the VisionFive is the closest device yet to the canceled BeagleV Starlight.
    https://www.hackster.io/news/dual-core-risc-v-linux-at-your-fingertips-hands-on-with-the-starfive-visionfive-v1-8gb-sbc-4af4a0c35492

    Reply
  4. Tomi Engdahl says:

    RISC-V-Based CORE-V MCU DevKit for IoT Launched
    July 19, 2022
    The CORE-V software developer kit with full-featured Eclipse integrated development environment and an open PCB design was first unveiled at embedded world in Nuremberg in June 2022.
    https://www.electronicdesign.com/technologies/iot/video/21246708/riscvbased-corev-mcu-devkit-for-iot-launched-at-dac-2022?utm_source=EG+ED+Connected+Solutions&utm_medium=email&utm_campaign=CPS220726116&o_eid=7211D2691390C9R&rdx.identpull=omeda|7211D2691390C9R&oly_enc_id=7211D2691390C9R

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  5. Tomi Engdahl says:

    Markkinoilla on jo yli 10 miljardia RISC-V-prosessoria
    Julkaistu: 01.08.2022
    https://etn.fi/index.php?option=com_content&view=article&id=13807&via=n&datum=2022-08-01_13:53:13&mottagare=30929

    10 miljardia prosessoria on valtava määrä. Esimerkiksi Arm-arkkitehtuurilta kesti 17 vuotta päästä tähän lukemaan. Avoimen lähdekoodin RISC-V-piirejä on kuitenkin toimitettu markkinoille jo 10 miljardia, kerto RISC-V International.

    Järjestön mukaan arkkitehtuurin menestys perustuu ennen kaikkea lähdekoodin avoimuuteen. RISC-V tekee saman raudalle, minkä Linux teki aiemmin ohjelmistoille.

    RISC-V-käskykanta perustuu 47:een 32-bittiseen käskyyn (RV32I). Perustason käskyjä voidaan vapaasti laajentaa laajennuskäskyillä. Osa laajennuksista on standardoitu ja esimerkiksi viime vuonna ratifioitiin 40 laajennusta.

    Tänä vuonna RISC-V International on esitellyt neljä uutta laajennusta. Yksi uusista on RISC-VUEFI Protocols, joka tuo nykyiset UEFI-standardit mukaan alustalle.

    Toisille yrityksille RISC-V on mahdollistanut uuden avun, kuten takavuosina esimerkiksi iPhonen grafiikkaprosessoreista tutulle Imagination Technologiesille. Nyt yhtiö kertoo tuovansa vielä tämän vuoden aikana markkinoille ensimmäisen RISC-V-arkkitehtuuriin perustuvan CPU-prosessorinsa.

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  6. Tomi Engdahl says:

    RISC-V

    RISC-V’s open-source Instruction Set Architecture (ISA) brings the possibility of endless customization and ease-of-use. Explore our wide range of technical content and see how RISC-V is paving a new way for computing design and innovation.

    https://www.mouser.com/empowering-innovation/more-topics/risc-v?utm_source=endeavor&utm_medium=display&utm_campaign=ed-personifai-eit2022-

    RISC-V

    RISC-V’s open-source Instruction Set Architecture (ISA) brings the possibility of endless customization and ease-of-use. Explore our wide range of technical content and see how RISC-V is paving a new way for computing design and innovation.
    The Tech Between Us Podcast
    RISC-V
    https://www.mouser.com/empowering-innovation/more-topics/risc-v?utm_source=endeavor&utm_medium=display&utm_campaign=mouser_eit-risc-v-podcast-audio#podcast-riscv

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  7. Tomi Engdahl says:

    RISC-V Serves Up Open-Source Possibilities for the Future
    July 12, 2022
    RISC-V offers a level of flexibility to design new processors because the instruction set isn’t defined at the ISA level, but rather is the compilation of the processor and other design parameters.
    https://www.electronicdesign.com/technologies/embedded-revolution/article/21246374/electronic-design-riscv-serves-up-opensource-possibilities-for-the-future?utm_source=EG+ED+Connected+Solutions&utm_medium=email&utm_campaign=CPS220718012&o_eid=7211D2691390C9R&rdx.identpull=omeda|7211D2691390C9R&oly_enc_id=7211D2691390C9R

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  8. Tomi Engdahl says:

    Markkinoilla on jo yli 10 miljardia RISC-V-prosessoria
    https://etn.fi/index.php?option=com_content&view=article&id=13807&via=n&datum=2022-08-01_13:53:13&mottagare=31202

    10 miljardia prosessoria on valtava määrä. Esimerkiksi Arm-arkkitehtuurilta kesti 17 vuotta päästä tähän lukemaan. Avoimen lähdekoodin RISC-V-piirejä on kuitenkin toimitettu markkinoille jo 10 miljardia, kerto RISC-V International.

    Järjestön mukaan arkkitehtuurin menestys perustuu ennen kaikkea lähdekoodin avoimuuteen. RISC-V tekee saman raudalle, minkä Linux teki aiemmin ohjelmistoille.

    RISC-V-käskykanta perustuu 47:een 32-bittiseen käskyyn (RV32I). Perustason käskyjä voidaan vapaasti laajentaa laajennuskäskyillä. Osa laajennuksista on standardoitu ja esimerkiksi viime vuonna ratifioitiin 40 laajennusta.

    Tänä vuonna RISC-V International on esitellyt neljä uutta laajennusta. Yksi uusista on RISC-VUEFI Protocols, joka tuo nykyiset UEFI-standardit mukaan alustalle.

    Reply
  9. Tomi Engdahl says:

    Exclusive CEO Interview: Latest Funding Drives Ventana’s First RISC-V Chiplets in Data Centers
    https://www.eetimes.com/exclusive-ceo-interview-latest-funding-drives-ventanas-first-risc-v-chiplets-in-data-centers/

    Ever since Ventana Micro Systems came out of stealth last year, the company has been busily developing relationships with partners and potential customers to create traction for its RISC-V–based chiplets, which it believes will address the high-performance computing demands in data centers and at the edge.

    Reply
  10. Tomi Engdahl says:

    Ubuntu Announces Compatibility With Second RISC-V System
    By Ian Evenden published about 15 hours ago

    Another Linux distro for the VisionFive
    https://www.tomshardware.com/news/ubuntu-official-for-visionfive-risc-v

    Reply
  11. Tomi Engdahl says:

    Dragon Li’s Bajiu Lite Is a Flexible FPGA Development Board with RISC-V SoC Capabilities
    Using the VexRiscv CRiscV soft-core, users can tailor the device for workloads ranging from computer vision to robotics.
    https://www.hackster.io/news/dragon-li-s-bajiu-lite-is-a-flexible-fpga-development-board-with-risc-v-soc-capabilities-543a7d768d54

    Reply
  12. Tomi Engdahl says:

    Intel yllätti: valmis alusta RISC-V-kehitykseen
    https://etn.fi/index.php?option=com_content&view=article&id=13945&via=n&datum=2022-08-31_15:10:15&mottagare=31202

    Intel on jo aiemmin sanonut tukevansa avoimeen lähdekoodiin perustuvien RISC-V-prosessorien kehitystä. Nyt yhtiö on lähtenyt tuumasta toimeen ja esitellyt valmiin kehitysalustan RISC-V-suunnitteluun. Mukana hankkeessa on koko joukko RISC-V-pioneereja.

    Intel Pathfinder on FPGA-pohjainen kortti. Se mahdollistaa useiden RISC-V-ytimien ja muiden IP-lohkojen testaamisen FPGA- ja simulaattorialustoilla, jolloin voidaan käyttää alan johtavia käyttöjärjestelmiä ja työkaluja yhtenäisessä IDE-ympäristössä.

    Reply
  13. Tomi Engdahl says:

    PINE64 has published the first pictures of its upcoming Star64 RISC-V single-board computer, a quad-core 64-bit Linux-capable gadget it hopes will offer competition to StarFive’s crowdfunded VisionFive 2.

    PINE64 Shows Off the First Star64 RISC-V Single-Board Computer Prototypes, Targets a Launch in Weeks
    https://www.hackster.io/news/pine64-shows-off-the-first-star64-risc-v-single-board-computer-prototypes-targets-a-launch-in-weeks-5d6983909a5d

    Board will arrive soon in 4GB and 8GB variants, but a functional operating system will rely on community contributions

    Reply
  14. Tomi Engdahl says:

    Engineering Academy Tackles RISC-V in Next Educational Event Installment
    Aug. 19, 2022
    The September 8 learning event from Electronic Design will feature in-depth coverage of RISC-V architecture, hardware, software, and a robust panel discussion.
    https://www.electronicdesign.com/technologies/embedded-revolution/article/21249088/electronic-design-engineering-academy-tackles-riscv-in-next-educational-event-installment?utm_source=EG+ED+Connected+Solutions&utm_medium=email&utm_campaign=CPS220830166&o_eid=7211D2691390C9R&rdx.identpull=omeda|7211D2691390C9R&oly_enc_id=7211D2691390C9R

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  15. Tomi Engdahl says:

    This blog attempts to summarize the key technical aspects and chip designer takeaways of the Intel Pathfinder for RISC-V initiative.
    http://arw.li/6184MKZa4
    #EDN #ChipDesigner

    https://www.edn.com/four-things-to-know-about-the-intel-pathfinder-for-risc-v/?utm_source=edn_facebook&utm_medium=social&utm_campaign=Articles

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  16. Tomi Engdahl says:

    Intel Pathfinder will allow a variety of RISC-V cores and other IPs to be instantiated on FPGA and simulator platforms. And it will do so while IPs utilize prominent operating systems and toolchains within a unified integrated development environment (IDE). That, in turn, saves time in assembling and testing different IP combinations in a single design environment.
    https://www.edn.com/four-things-to-know-about-the-intel-pathfinder-for-risc-v/?utm_source=edn_facebook&utm_medium=social&utm_campaign=Articles

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  17. Tomi Engdahl says:

    https://etn.fi/index.php/13-news/13980-risc-v-tuli-moottorinohjaukseen

    Avoimen RISC-V-arkkitehtuurin suosio kasvaa nyt kiihtyvällä vauhdilla. Jo aiemmin arkkitehtuuriin perustuville ohjaimille tukensa esittänyt Renesas on esitellyt markkinoiden ensimmäisen RISC-V-pohjaisen mikro-ohjaimen, joka on optimoitu erityisesti edistyneille moottorinohjausjärjestelmille.

    R9A02G020-ohjain on valmiiksi esiohjelmoitu, ”avaimet käteen” -tyyppinen sovellusprosessori. Asiakkaan ei tarvitse investoida RISC-V-kehitykseen liittyviin työkaluihin ja ohjelmistoihin. Ohjainpiirin kohdesovelluksia ovat koti- ja rakennusautomaatio, terveydenhuollon laitteet, kodinkoneet, droonit ja monet muut sulautetut laitteet.

    Renesas esitteli jokin aika sitten 64-bittiset yleiskäyttöiset RZ/Five MPU:t, jotka perustuvat 64-bittiseen RISC-V-suorittimeen. R9A02G020-ohjain perustuu Andes Technologyn prosessori-IP:een.

    https://www.renesas.com/us/en/products/microcontrollers-microprocessors/risc-v/r9a02g020-assp-easy-mcu-motor-control-based-risc-v

    Reply
  18. Tomi Engdahl says:

    Pinecil V2 Review: Smart Soldering Iron, Powered by RISC-V CPU
    Low cost soldering iron, with high end features.
    https://www.tomshardware.com/reviews/pinecil-v2

    Reply
  19. Tomi Engdahl says:

    RISC-V valloittaa seuraavaksi avaruuden
    https://etn.fi/index.php/13-news/13992-risc-v-valloittaa-seuraavaksi-avaruuden

    Avoimeen arkkitehtuuriin perustuvat RISC-V-piirit ovat valloittamassa nopeasti sulautettujen laitteiden markkinoita. Seuraavaksi vuorossa on avaruus. NASA on valinnut SiFiven RISC-V-piirit seuraavan sukupolven avaruusmatkailun prosessorialustaksi.

    SiFive kertoo, että nykyisiin laskenta-alustoihin verrattuna sen X280-prosessori tarjoaa 100-kertaisen lisäyksen laskentakapasiteetissa. NASAn seuraavan sukupolven HPSC-alustaa (High-Performance Spaceflight Computing) tullaan käyttämään käytännössä kaikissa tulevissa avaruustehtävissä planeettojen tutkimisesta kuun ja Marsin pintatehtäviin.

    HPSC hyödyntää kahdeksaa X280 RISC-V-vektoriydintä ydintä sekä neljää muuta SiFiven RISC-V -ydintä tarjotakseen 100-kertaisen laskentakyvyn nykypäivän avaruustietokoneisiin verrattuna. Tämä laskentasuorituskyvyn valtava kasvu auttaa avaamaan uusia mahdollisuuksia erilaisille tehtäväelementeille, kuten autonomisille rovereille, kuvankäsittelylle, avaruuslennoille, opastusjärjestelmille, tietoliikenteelle ja muille sovelluksille.

    SiFiven liiketoiminnan kehitysjohtaja Jack Kangin mukaan X280:n suorituskyky tuo suuria parannuksia kilpailevaan prosessoriteknologiaan verrattuna, ja SiFive RISC-V IP antaa NASAlle mahdollisuuden hyödyntää nopeasti kasvavan globaalin RISC-V-ekosysteemin tukea, joustavuutta ja pitkän aikavälin elinkelpoisuutta. – Olemme aina sanoneet, että SiFiven tulevaisuudella ei ole rajoja, ja olemme innoissamme nähdessämme innovaatioidemme vaikutuksen ulottuvan kauas planeettamme ulkopuolelle.

    Reply
  20. Tomi Engdahl says:

    Ztachip open-source RISC-V AI accelerator performs up to 50 times faster
    https://www.cnx-software.com/2022/09/12/ztachip-open-source-risc-v-ai-accelerator-performs-up-to-50-times-faster/

    Ztachip is an open-source RISC-V accelerator for vision and AI edge applications running on low-end FPGA devices or custom ASIC that is said to perform 20 to 50 times faster than on non-accelerated RISC-V implementations, and is also better than RISC-V cores with vector extensions (no numbers were provided here).

    Reply
  21. Tomi Engdahl says:

    Featuring USB Type-C connectivity, JTAG debugging, Wi-Fi, Bluetooth, and battery management, this board packs in the features.

    Olimex Launches New ESP32-C3-DevKit-LiPo RISC-V Development Board for Under $6
    https://www.hackster.io/news/olimex-launches-new-esp32-c3-devkit-lipo-risc-v-development-board-for-under-6-47911a895199

    Bulgarian open source hardware specialist Olimex has launched a new compact development board, built around the RISC-V Espressif ESP32-C3: the ESP32-C3-DevKit-Lipo.

    Designed to cram in the features without bloating the cost, Olimex’ ESP32-C3-DevKit-Lipo is described by company founder Tsvetan Usunov as an “entry-level RISC-V board,” yet includes an impressive 15 general-purpose input/output (GPIO) pins, 2.4GHz 802.11/b/g/n Wi-Fi and Bluetooth 5 connectivity with an on-board antenna, and an integrated lithium-polymer battery management system with status LED.

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  22. Tomi Engdahl says:

    PINE64 has announced a new low-cost single-board computer based on the Bouffalo LAb BL808 RISC-V SoC: the compact Ox64, with an unusual dual-core 32-bit/64-bit split design.

    PINE64 Unveils the Ox64, a Low-Cost Dual-Core RISC-V Single-Board Computer with Breadboard Support
    https://www.hackster.io/news/pine64-unveils-the-ox64-a-low-cost-dual-core-risc-v-single-board-computer-with-breadboard-support-36465495dcbe

    With 64MB of RAM and up to 16MB of flash, this low-cost embedded machine features an unusual chip design.

    Reply
  23. Tomi Engdahl says:

    Report: Apple to Move a Part of its Embedded Cores to RISC-V, Stepping Away from Arm ISA
    https://www.techpowerup.com/298936/report-apple-to-move-a-part-of-its-embedded-cores-to-risc-v-stepping-away-from-arm-isa

    According to Dylan Patel of SemiAnalysis sources, Apple is moving its embedded cores from Arm to RISC-V. In Apple’s Silicon designs, there are far more cores than the main ones that power the operating system and end-user applications. For example, embedded cores are present, and there are 30+ in M1 SoCs responsible for all kinds of workloads not related to the operating system. These tasks are usually associated with other functions such as WiFi/BlueTooth, ThunderBolt retiming, touchpad control, NAND chips having their own core, etc. They run their own firmware and power everything around the central cores that run the OS, so the whole SoC functions appropriately.

    It appears that a lot of these cores are based on Arm M-series or lower-end A-series IP that Apple is currently looking to replace with RISC-V.

    Given that a large portion of software runs on the main big.LITTLE configuration, other secondary SoC tasks can migrate to a different ISA like RISC-V, with a small firmware adjustment. Given that these cores can be placed with custom IPs, Apple would save licensing fees if custom RISC-V cores were used.

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  24. Tomi Engdahl says:

    Researchers Build a RISC-V Chip That Calculates in Posits, Boosting Accuracy for ML Workloads
    Designed as an alternative to floating-point numbers, posits may prove key to boosting machine learning performance.
    https://www.hackster.io/news/researchers-build-a-risc-v-chip-that-calculates-in-posits-boosting-accuracy-for-ml-workloads-086b985bf0c1

    Reply
  25. Tomi Engdahl says:

    https://etn.fi/index.php/13-news/14124-tiukempaa-c-koodia-riscv-prosessorille

    Sulautettujen sovellusten suorituskyky riippuu monesta tekijästä. Yksi niistä on koodin optimointi, joka vaikuttaa sekä nopeuteen että muistinkäyttöön. RISC-V-pioneeri SiFive on nyt lisensoinut SEGGERin kirjaston oman koodinsa suorituskyvyn parantamiseen.

    SiFive on lisensoinut SEGGERiltä emRun++ -kirjaston RISC-V-prosessoriensa C++-kielen optimointiin. emRun++ on kattava C++-standardikirjasto, joka on erityisesti suunniteltu ja optimoitu GCC/LLVM-pohjaisille työkaluketjuille ja sulautetuille järjestelmille. Se perustuu SEGGERin tehokkaisiin emRun- ja emFloat-ajonaikaisiin ja liukulukukirjastoihin.

    SiFiven mukaan emRun++kirjasto tuottaa tiukempaa ja suorituskykyisempää koodia kuin tarjolla olevat avoimen lähdekoodin vaihtoehdot.

    Reply
  26. Tomi Engdahl says:

    Taas läpimurto: RISC-V-prosessori sertifioitiin autojen kriittisiin sovelluksiin
    https://etn.fi/index.php/13-news/14127-taas-laepimurto-risc-v-prosessori-sertifioitiin-autojen-kriittisiin-sovelluksiin

    Taiwanilainen Andes Technology tunnetaan yhtenä avoimien RISC-V-prosessorien pioneereista. Nyt Andes ilmoittaa merkittävästä läpimurrosta, kun sen N25F-SE-ydin on sertifioitu autoelektroniikan vaativan ISO26262-standardin mukaisesti.

    Saksalainen SGS-TÜV Saar auditoi Andesin ytimen ja sen mukaan ydin täyttää autoelektroniikan turvallisuutta määrittelevien ASIL B -vaatimusten osat 2,4,5, 8 ja 9. Tämä tarkoittaa, että ydintä voidaan käyttää laitteissa, jotka huolehtivat ajoneuvojen B-tason järjestelmissä. Tämä tarkoittaa esimerkiksi avaimetonta käynnistystä, kojelaudan ohjausta, rengaspaineiden valvontaa, valojen ohjausta ja ADAS-kameroiden hallintaa.

    N25F-SE on 32-bittinen RISC-V-ydin, joka tukee tavallisia IMACFD-laajennuksia, kokonaislukuja, liukulukukäskyjä sekä Andesin omia V5 -laajennuksia

    ASIL-järjestelmä on neliportainen, jossa A edustaa alinta vaatimustasoa ja D ylintä. Ylimmän D-tason järjestelmiä ovat esimerkiksi turvatyynyt, lukkiutumattomat jarrut ja ohjaustehostin, eli kaikki kriittisimmät turvajärjestelmät.

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  27. Tomi Engdahl says:

    10 cents CH32V003 RISC-V MCU offers 2KB SRAM, 16KB flash in SOP8 to QFN20 packages
    WCH CH32V003 is a new ultra-cheap RISC-V microcontroller (MCU) clocked at 48 MHz with 2KB SRAM, 16KB flash, and a bunch of interfaces that sells for under 10 cents in quantities.
    https://www.cnx-software.com/2022/10/22/10-cents-ch32v003-risc-v-mcu-offers-2kb-sram-16kb-flash-in-sop8-to-qfn20-packages/

    Reply
  28. Tomi Engdahl says:

    The advent of the RISC-V instruction set has given the design engineer a solid basis for system design with a standard core and standard or custom extensions using an FPGA. The instruction set is both open and frozen, and processor designs will continue to work well even as RISC-V evolves.
    https://www.mouser.com/empowering-innovation/more-topics/risc-v?utm_source=endeavor&utm_medium=display&utm_campaign=ed-personifai-eit2022-#article2-riscv

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  29. Tomi Engdahl says:

    RISC-V on pian valmis älypuhelimiin
    https://etn.fi/index.php/13-news/14195-risc-v-on-pian-valmis-aelypuhelimiin

    SiFive on yksi avoimeen RISC-V-arkkitehtuuriin perustuvien suoritinytimien kehittäjien kärkinimistä. Nyt yhtiö on esitellyt kaksi uutta ydintä, jotka sopivat erityisesti puettaviin laitteisiin. Aivan kännykkäprosessoreja SiFiven ytimillä ei vielä tehdä, mutta sekään aika ei ole enää kaukana.

    P670- ja P470-prosessorit tuovat selvästi aiempaa enemmän suorituskykyä ja energiatehokkuutta yhtiön valikoimaan. Erityisesti suorituskyvyssä on otettu iso hyppäys eteenpäin. Ne tukevat esimerkiksi virtualisointia, vektorilaajennuskäskyjä ja ensimmäistä kertaa RISC-V-maailmassa vektorisalauksen laajennuksia.

    Uutuuksista P670-prosessori yltää 5 nanometrin prosessissa toteutettuna yli 3,4 gigahertsin kellotaajuuteen. Vektorilaskentaa prosessorilla on kaksi 128-bittistä ALU-yksikköä. P470 on puolestaan ensimmäinen erityisesti energiatehokkaaksi suunniteltu RISC-V-prosessori.

    Reply
  30. Tomi Engdahl says:

    RISC-V: The Instruction-Set Alternative
    RISC-V is an open-source processor instruction set that has been adopted by a wide range of chip and software vendors.
    https://www.electronicdesign.com/magazine/50430

    Reply
  31. Tomi Engdahl says:

    Pine64′s RISC-V Ox64 Takes On Raspberry Pi Pico W
    By Ian Evenden published October 10, 2022
    Powerful Pico Proxy
    https://www.tomshardware.com/news/pine64-ox64-risc-v-pico-alternative

    Reply
  32. Tomi Engdahl says:

    WCH Launches a Sub-10¢ RISC-V Microcontroller, While a $6.90 Dev Board Gets You Started
    Designed for less-computationally-demanding workloads, this 32-bit RISC-V chip is priced extremely aggressively.
    https://www.hackster.io/news/wch-launches-a-sub-10-risc-v-microcontroller-while-a-6-90-dev-board-gets-you-started-90b1ffd7490a

    Reply
  33. Tomi Engdahl says:

    Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications
    https://www.cnx-software.com/2022/11/03/andes-andescore-ax60-out-of-order-risc-v-core-for-compute-intensive-applications/

    Andes Technology has unveiled the high-end AndesCore AX60 series out-of-order 64-bit RISC-V processors at the Linley Fall Processor Conference 2022 with the new cores designed for compute-intensive applications such as advanced driver-assistance systems (ADAS), artificial intelligence, augmented/virtual reality, datacenter accelerators, 5G infrastructure, high-speed networking, and enterprise storage.

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  34. Tomi Engdahl says:

    Efinix Launches RISC-V-Based TinyML Platform for High-Efficiency Edge AI Acceleration
    https://www.hackster.io/news/efinix-launches-risc-v-based-tinyml-platform-for-high-efficiency-edge-ai-acceleration-77cd348dc477

    Built on the 32-bit VexRiscv core with custom instructions, this TFLite Micro platform offers the option of user-defined acceleration.

    Reply
  35. Tomi Engdahl says:

    Compact RISC-V Cores Bring the Power to Wearables, Consumer Devices
    Nov. 10, 2022
    The latest RISC-V CPU cores from SiFive, the P670 and P470, are targeted at applications where compute density matters.
    https://www.electronicdesign.com/technologies/embedded-revolution/article/21254516/electronic-design-compact-riscv-cores-bring-the-power-to-wearables-consumer-devices?utm_source=EG+ED+Connected+Solutions&utm_medium=email&utm_campaign=CPS221103039&o_eid=7211D2691390C9R&rdx.identpull=omeda|7211D2691390C9R&oly_enc_id=7211D2691390C9R

    SiFive is expanding its family of high-end RISC-V CPU cores, aiming to unseat Arm’s Cortex-A series in space-constrained, performance-hungry designs such as wearables, robots, and other consumer devices.

    The Santa Clara, California-based company said one of the new 64-bit cores, the P670, is its most advanced CPU yet based on the RISC-V architecture. It will compete with Arm’s Cortex-A78 processor, which made it into smartphones chips for the first time in 2019. SiFive indicated that the P670 is best suited for a 5-nm process node and packs roughly the same performance as the Cortex-A78 in a 50% smaller space.

    To complement it, the company also rolled out the P470 core. It features many of the same building blocks as the P670 in a more compact, less power-hungry package that will compete directly with Arm’s Cortex-A55.

    Reply
  36. Tomi Engdahl says:

    RISC-V-koodista tehokkaampaa pakkaamalla
    https://etn.fi/index.php/13-news/14273-risc-v-koodista-tehokkaampaa-pakkaamalla

    Ruotsalainen IAR Systems ilmoittaa ottaneensa RISC-V-prosessorien kehitystyökaluunsa Andes Technologyn kehittämän laajennuksen, jolla voidaan pienentää koodin kokoa ja tehdä siitä suorituskykyisempää. CoDense-laajennus on jo mukana IAR Embedded Workbench for RISC-V -työkalujen uudessa 3.11-versiossa.

    CoDense on patentoitu prosessorin käskykannan laajennus, jota on jo käytetty yli 10 miljardissa AndesStar V3 -laajennuksia hyödyntävässä piirissä. Lisäksi IAR toi työkaluihinsa tuen tekniikalle, joka pakkaa SIMD-käskyjä pienempään tilaan. Myös symmetrinen ja asymmetrinen multiprosessointi nopeutuu koodia pakkaamalla.

    https://www.iar.com/riscv

    Reply
  37. Tomi Engdahl says:

    Ubuntu Bring-Up Happening For The StarFive VisionFive 2 RISC-V Board
    https://www.phoronix.com/news/Ubuntu-StarFive-VisionFive-2

    Reply
  38. Tomi Engdahl says:

    Combining RISC-V and FPGA Offers New Design Solutions
    https://www.mouser.com/empowering-innovation/more-topics/risc-v?utm_source=endeavor&utm_medium=display&utm_campaign=ed-personifai-eit2022-#article2-riscv

    The advent of the RISC-V instruction set has given the design engineer a solid basis for system design with a standard core and standard or custom extensions using an FPGA. The instruction set is both open and frozen, and processor designs will continue to work well even as RISC-V evolves.

    https://resources.mouser.com/eit/combining-risc-v-and-fpga-offers-new-design-solutions

    Microchip offers RISC-V processing in two PolarFire families (plus one rad-tolerant type). Both offer processor options suitable for RISC-V implementation. All of the devices are non-volatile, instant-on. They have four to twenty-four optimized 12.7Gbit/s transceivers that are said to require 1/2 the power vs. competing products, plus DDR4 and 1.6Gbit/s LVDS interfaces. The chips offer a system controller suspend mode for safety-critical designs and many security features.

    PolarFire MPFxxxT FPGAs come in 50k, 100k, 200k, 300k, and 500k logic element (LE) versions—with the option of a Mi-V RISC-V soft core processor. An essential CPU core uses up to about 10k LEs. The chips’ integrated hard IP includes a dual PCIe endpoint/root port, PLLs, DLLs, an 18 x 18 MACC pre-adder, and a crypto processor.

    A few examples of the more than 100 available application-specific extensions would be a finite impulse response (FIR) Filter, a CRC32 (32-bit cyclic redundancy check), and 3DES (Triple Data Encryption Standard) algorithms. Adding extensions to a RISC-V core performance on these functions can be significantly accelerated while saving considerable power.

    Reply
  39. Tomi Engdahl says:

    Existing in a single 400-line header file, this RISC-V emulator can boot a usable Linux operating system and run executables.

    Charles Lohr’s Linux-Capable Really Tiny RISC-V Emulator Exists in a Single 400-Line C Header File
    https://www.hackster.io/news/charles-lohr-s-linux-capable-really-tiny-risc-v-emulator-exists-in-a-single-400-line-c-header-file-7d7801cf042c

    Existing in a single 400-line header file, this RISC-V emulator can boot a usable Linux operating system and run executables.

    Electrical engineer Charles Lohr has built a 32-bit RISC-V emulator with a difference: it exists as a single C header file, of around 400 lines of code — yet is capable of running Linux, despite a lack of memory management unit (MMU).

    “I’ve been working really hard over the last few weeks on this little tiny RISC-V emulator. The really tiny part about is is that it doesn’t have an MMU which is something that virtually all desktop modern processors have,” Lohr explains. “The reason I wanted to do this was I wanted to see if I could run Linux on it. Something that was close to but not as simple as an ESP32-C3. And well the answer was. Yes. In fact I was able to write a really tiny RISC-V emulator. The actual emulator part all exists in this one function in this header file and it was only around 350, 400 lines of code. And it’s able to run Linux and I’m able to have executables and whatever on it.”

    The emulator, mini-rv32ima, implements the 32-bit RV32IMA variant of the RISC-V architecture, plus the Zifencei and Zicsr extensions. What it doesn’t implement is a memory management unit (MMU), which is something the Linux kernel expects to see

    The resulting emulator is tiny indeed: coming in at around 400 lines of code, it exists in a single C header file without a single external dependency — “not even libc,” Lohr notes. It clocks in at around half the speed of the considerably larger QEMU emulator, can be easily embedded in other applications — and once compiled with its demo wrapper, which adds a further 250 lines of code to support a command-line interface, system control interface, UART serial bus, device tree, and kernel image loader, comes out as a single executable just 18kB in size or less when compressed.

    The source code for the project has been published to GitHub under the permissive MIT, BSD three-clause, and Creative Commons Zero licenses.

    https://github.com/cnlohr/mini-rv32ima

    Reply
  40. Tomi Engdahl says:

    Intel Pathfinder for RISC-V unifies platform, adds features
    https://www.edn.com/intel-pathfinder-for-risc-v-unifies-platform-adds-features/

    Intel Pathfinder for RISC-V—a pre-silicon development environment that supports IP selection via testing for compatibility and performance—is unifying its Starter and Professional Editions into a single version. Intel is expected to share more details about this unification at the RISC-V Summit in San Jose, California on 12-15 December 2022.

    Intel Pathfinder for RISC-V, which aids system-on-chip (SoC) designers with early-stage software development using FPGA and simulator platforms, was initially made available in two versions. The Starter Edition, intended for the hobbyist, academia and research community, has been available as a free download. The Professional Edition, which came with broad ecosystem support, targeted organizations involved in commercial RISC-V based silicon and software.

    Reply

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