Can RISC-V – Linux of Microprocessors – Start an Open Hardware Renaissance?

RISC-V is an interesting open hardware CPU. It is the most promising open CPU design, but can it succeed in competitive CPU market? 


  1. Tomi Engdahl says:

    Layoffs at SiFive as RISC-V upstart turns focus to custom cores

    Layoffs at SiFive as RISC-V upstart faces a crossroads

    SiFive, a prominent player in the RISC-V design arena, is going through a radical makeup. While layoffs at one of the early RISC-V startups are making headlines in trade media, what’s happening underneath is a significant shift in its business model.

    The well-funded RISC-V upstart built its business around two product lines. First, pre-designed and silicon-proven RISC-V cores that designers can pick to develop their system-on-chips (SoCs). SiFive has been shipping these ready-made RISC-V cores along with a debugging tool that can be used to test the reliability of an SoC design before manufacturing.

    Second, custom cores that SiFive designed with specific requirements; these custom cores are later installed into an SoC. The news behind this layoff story is that SiFive is dumping its low-cost RISC-V core business to focus on custom cores.

    Still, layoffs have been massive. Though media reports vary on numbers ranging from 100 to more than 300, design engineers have borne the brunt of this restructuring.

  2. Tomi Engdahl says:

    Linux on Scratch Is Proven Possible, Thanks to This Clever RISC-V Emulator Project

    Running a Scratch port of Charles Lohr’s RISC-V emulator, this clever project achieves the seemingly impossible.

    Pseudonymous developer “bilman66″ has achieved the seemingly impossible by getting a Linux operating system to boot in the Scratch visual coding environment — by writing a Scratch RISC-V emulator.

    “A real build of the Linux 6.1.14 kernel running in pure Scratch code,” bilman66 writes of their creation, brought to our attention by Adafruit. “The Linux build comes with the usual programs like cat/echo and is fully capable of running shell scripts, but it also comes with Duktape (a JavaScript engine), as well as ed for text editing, and CoreMark for benchmarking.”

  3. Tomi Engdahl says:

    Qualcomm Partners with Google to Launch a First-Class RISC-V Platform for Wear OS Wearables
    Two months after announcing a RISC-V joint venture, Qualcomm looks to make the architecture the go-to for performance wearables.

  4. Tomi Engdahl says:

    Prokyber’s ESP32-C6-Bug Is a Compact RISC-V Dev Board for IoT Projects with Matter and More
    With 19 GPIO pins exposed, surface-mount support, and radios for Wi-Fi 6, BLE, and Zigbee/Threads, this board is ready for the IoT.

  5. Tomi Engdahl says:

    SiFive Aims at RISC-V Generative AI, ML with Its New Performance P870, Intelligence X390 Cores
    Aims to pair its new scalar and vector compute cores to drive generative artificial intelligence workloads and more.

  6. Tomi Engdahl says:

    Google plans RISC-V Android tools in 2024, wants developers to “be ready”
    We’ve got RISC-V OS support, incoming chips, and soon, an app ecosystem.

  7. Tomi Engdahl says:

    AMD MicroBlaze™ V Processor
    A Flexible and Efficient RISC-V Processor.

  8. Tomi Engdahl says:

    GigaDevice Unveils a 160MHz Wi-Fi 6-Capable RISC-V “Combo Wireless” Microcontroller, the GD32VW553
    A single 32-bit core is joined by 288kB of dedicated SRAM, up to 4MB of on-chip flash, and a radio which does Wi-Fi 6 and BLE 5.2.

  9. Tomi Engdahl says:

    Leading Semiconductor Industry Players Join Forces to Accelerate RISC-V
    Establishing a new company to drive RISC-V ecosystem and hardware development

  10. Tomi Engdahl says:

    RISC-V Specialist Milk-V Jumps Into the Network Market with the New 10-gig-E Vega Switch
    Offering the promise of an open source Linux-based software environment, this 14-port switch includes two 10-gig-Ethernet SFP+ ports.

  11. Tomi Engdahl says:

    China in a bull shop: One of the largest Chinese tech companies has announced a ‘game-changing’ 3,072-core RISC-V server that used an indigeneous CPU — on US soil
    By Keumars Afifi-Sabet published 3 days ago
    China hits a key milestone with Alibaba demonstrating the first cloud server powered by a RISC-V chip

  12. Tomi Engdahl says:

    Renesas Goes In-House, Unveils Its First Home-Brand RISC-V MCU Core — with Silicon Due Early 2024
    Company’s existing shift away from Arm to RISC-V in selected products gathers pace, with its first homebrew RISC-V core design.

  13. Tomi Engdahl says:

    Christmas ornament based on CH32V003 (RISCV MCU)
    Harnessing the power and simplicity of the CH32V003 microcontroller to create a luminous ornament for decorating a Christmas tree.

  14. Tomi Engdahl says:

    OLEDscope Demonstrates That Vector-Based Displays Are Not Limited to CRTs Anymore!
    Single-pixel images drawn on a 128×128 OLED by a 10-cent 32-bit RISC-V microcontroller.

  15. Tomi Engdahl says:


    Like many of you, we’ve been keeping a close eye on the CH32 family of RISC-V microcontrollers from WCH Electronics. You can get the CH32V003, featuring 2 kB RAM and 16 kB of flash for under fifteen cents, and the higher-end models include impressive features like onboard Ethernet. But while the hardware is definitely interesting, the software side of things has been a little rocky compared to what we’ve come to expect from modern MCUs.

    Things should start looking up a bit though with the release of an Arduino core for the CH32 direct from WCH themselves. It’s been tested on Windows, Linux, and Mac, and supports the CH32V00x, CH32V10x, CH32V20x, CH32V30x, and CH32X035 chips.

  16. Tomi Engdahl says:

    Hangover Aiming For RISC-V Support This Year, x86_64 Emulation

    Building off this week’s release of Wine 9.0 for running Windows games and applications on Linux and other platforms is now Hangover 9.0. Hangover as a reminder is the project based on Wine initially focused on running x86 32-bit Windows apps on AArch64 Linux. Hangover works by running Wine atop various emulators such as QEMU, FEX, or Box64 for handling the processor/ISA translation.

    Hangover 9.0 is now available and has Wine 9.0 plus the latest goodies on the Hangover side. Hangover in recent months has seen QEMU support for WOW64 emulation, improved FEX support, Box64 support was fully integrated, Debian packages, and continuing to prove the performance and capabilities of Hangover

  17. Tomi Engdahl says:

    LicheeRV Nano – A low-cost SG2002 RISC-V and Arm camera and display board with optional WiFi 6 and/or Ethernet

  18. Tomi Engdahl says:

    Sipeed Lichee Console 4A Review: Tiny RISC-V Laptop Has a Pointing Stick
    A tiny laptop for RISC-V development

  19. Tomi Engdahl says:

    Microchipin uusi PolarFire SoC Discovery -kehityssarja lupaa tehdä RISC-V- ja FPGA-suunnittelusta aiempaa helpompaa. Vastaavia kaupallisia kehityssarjoja ja piirejäkin on vasta varsin rajoitetusti tarjolla.

    Discovery Kit rakentuu Microchipin PolarFire MPFS095T SoC FPGA -järjestelmäpiirin ympärille, joka sisältää kaikkiaan neljä 64-bittistä RISC-V Instruction Set Architecture (ISA) -arkkitehtuuriin perustuvaa prosessoriydintä sekä 95 000 ohjelmoitavaa FPGA-logiikkaelementtiä.

  20. Tomi Engdahl says:

    The ThingPulse ePulse Feather C6 RISC-V Development Board Promises an ~18µA Low-Power Sleep Mode
    Designed for bursty battery-powered Internet of Things (IoT) projects, this low-power dev board can deliver a long runtime per charge.

  21. Tomi Engdahl says:

    Firm headed by legendary chip architect behind AMD Zen finally releases first hardware — days after being selected to build the future of AI in Japan, Tenstorrent unveils Grayskull, its RISC-V answer to GPUs
    By Wayne Williams published March 10, 2024
    Grayskull-powered DevKits are available to two versions – e75 and e150

  22. Tomi Engdahl says:

    HPMicro HPM6800 600 MHz RISC-V MCU comes with a Vivante 2.5D GPU with OpenVG support
    HPMicro HPM6800 is a family of high-end RISC-V microcontrollers clocked up to 600 MHz integrating a VeriSilicon Vivante 2.5D GPU with support for the OpenVG 1.1 vector graphics API, and peripherals making it suitable for digital dashboard displays and human-machine interfaces (HMI).

  23. Tomi Engdahl says:

    HPMicro HPM6800 600 MHz RISC-V MCU comes with a Vivante 2.5D GPU with OpenVG support
    HPMicro HPM6800 is a family of high-end RISC-V microcontrollers clocked up to 600 MHz integrating a VeriSilicon Vivante 2.5D GPU with support for the OpenVG 1.1 vector graphics API, and peripherals making it suitable for digital dashboard displays and human-machine interfaces (HMI).

  24. Tomi Engdahl says:

    Vlad Tomoiagă Puts Linux on the $0.15 WCH CH32V003 RISC-V Microcontroller
    Using Charles Lohr’s 400-line RISC-V emulator, the low-cost CH32V003 is able to run code designed for considerably costlier parts.

  25. Tomi Engdahl says:

    X-Silicon on uusi Piilaakson veteraanien perustama yritys, joka aikoo mullistamaan GPU-suunnittelun RISC-V-pohjaisella vektori-grafiikkalaskentamoottorilla. Se pystyy suorittamaan rinnakkain tekoäly-, HPC- ja 2D/3D-grafiikkatehtäviä.

  26. Tomi Engdahl says:

    The Arm-and-RISC-V RVAM16 Aims to Make It Easier to Move From One Embedded Architecture to Another
    Designed for the embedded space, RVAM16 can run either RISC-V or Arm Thumb binaries with little performance penalty.


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